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Entry Level Ic Layout Design Engineer Jobs in Washington, DC

CRB

HVAC Design Engineer

Rockville, MD · On-site

This individual may also delegate basic and fundamental tasks to entry-level engineers and designers. Responsibilities * Interfaces with clients and external partners. * Develops design and ...

CRB

HVAC Design Engineer

Rockville, MD · On-site

This individual may also delegate basic and fundamental tasks to entry-level engineers and designers. Responsibilities * Interfaces with clients and external partners. * Develops design and ...

Axon

Electrical Engineer I

Sterling, VA

This is an entry-level Electrical Engineer role for someone who wants to build hardware with their ... The rest is design work alongside senior engineers, starting with cables, harnesses, and PCB layout ...

New

Actalent

Civil Engineer - Entry Level

Ashburn, VA

$60K - $75K/yr

Civil Design Engineer / CAD Technician The Civil Design Engineer / CAD Technician will support land development projects in the Ashburn, VA area, focusing on the design of industrial, commercial, and ...

Sargent & Lundy

Entry Level Civil Engineer

Elkridge, MD

$62K - $90K/yr

... entry-level position will offer you the opportunity to utilize and expand your civil engineering ... Prepare site layout, grading, and drainage designs. * Design storm sewer systems, roads, trackwork ...

Sargent & Lundy

Entry Level Civil Engineer

Elkridge, MD

$62K - $90K/yr

... entry-level position will offer you the opportunity to utilize and expand your civil engineering ... Prepare site layout, grading, and drainage designs. * Design storm sewer systems, roads, trackwork ...

Alarm.com

Device Engineer II (RF/EMC)

Tysons Corner, VA · On-site

HW engineering design experience including schematic capture, layout design, and hardware bring-up. * Experience conducting simulation using Ansys SIwave and HFSS software. * Master of Science degree ...

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Showing results 21-40

All JobsIc Layout Design Engineer JobsEntry Level Ic Layout Design Engineer JobsEntry Level Ic Layout Design Engineer Jobs in Washington, DC

Entry Level Ic Layout Design Engineer information

See Washington, DC salary details

$51K

$136.9K

$210.1K

How much do entry level ic layout design engineer jobs pay per year?

As of Aug 20, 2026, the average yearly pay for entry level ic layout design engineer in Washington, DC is $136,873.00, according to ZipRecruiter salary data. Most workers in this role earn between $101,900.00 and $163,100.00 per year, depending on experience, location, and employer.

What does an entry level IC layout design engineer do?

An Entry Level IC Layout Design Engineer is responsible for creating the physical layout of integrated circuits (ICs) based on circuit schematics provided by design engineers. They use specialized software tools to translate schematic diagrams into precise geometries that can be manufactured on silicon chips. Their tasks include floorplanning, placement, routing, and verifying layouts to ensure they meet design specifications and manufacturing requirements. They often work closely with circuit designers and verification teams to optimize performance and minimize errors. Attention to detail and knowledge of semiconductor fabrication processes are essential in this role.

What are the key skills and qualifications needed to thrive as an entry level IC layout design engineer?

To thrive as an Entry Level IC Layout Design Engineer, you need a solid background in electrical engineering concepts, semiconductor physics, and integrated circuit (IC) design principles, typically with a relevant bachelor's degree. Familiarity with industry-standard EDA tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys, as well as basic scripting languages, is highly beneficial. Attention to detail, problem-solving ability, and effective communication are crucial soft skills for collaborating with design teams and ensuring design accuracy. These skills and qualities are essential for producing high-quality, manufacturable layouts while meeting technical specifications and project deadlines.

What are some common challenges faced by entry level IC layout design engineers during their first year on the job?

Entry Level IC Layout Design Engineers often encounter challenges such as mastering complex Electronic Design Automation (EDA) tools, understanding intricate design rules, and balancing speed with accuracy in layout creation. Navigating the verification and sign-off processes, as well as effectively communicating with senior engineers and cross-functional teams, can also be demanding initially. However, with mentorship and hands-on experience, most new engineers quickly develop confidence and proficiency in these areas.

What is the difference between Entry Level Ic Layout Design Engineer vs Entry Level IC Design Engineer?

AspectEntry Level IC Layout Design EngineerEntry Level IC Design Engineer
Primary FocusPhysical layout, placement, routing of integrated circuitsHigh-level circuit design, architecture, and functional verification
Skills RequiredEDA tools, layout design, knowledge of fabrication processesCircuit theory, HDL coding, simulation tools
Work EnvironmentDesign teams in semiconductor companies, fabrication facilitiesDesign teams, EDA tool environments, simulation labs
Common CertificationsNone specific, but familiarity with CAD tools preferredNone specific, but knowledge of digital/analog design certifications helpful

In summary, Entry Level IC Layout Design Engineers focus on the physical implementation of integrated circuits, working with layout and fabrication processes. In contrast, Entry Level IC Design Engineers concentrate on circuit functionality and high-level design. Both roles are essential in semiconductor development and often collaborate closely.

What are popular job titles related to Entry Level Ic Layout Design Engineer jobs in Washington, DC?

For Entry Level Ic Layout Design Engineer jobs in Washington, DC, the most frequently searched job titles are:

What job categories do people searching Entry Level Ic Layout Design Engineer jobs in Washington, DC look for?

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Entry Level Ic Layout Design Engineer jobs near you
Infographic showing various Entry Level Ic Layout Design Engineer job openings in Washington, DC as of June 2026, with employment types broken down into 96% Full Time, and 4% Contract. Highlights an 86% In-person, 9% Hybrid, and 5% Remote job distribution, with an average salary of $136,873 per year, or $65.8 per hour.

Associate Electronic and Optical Materials Device Fabrication Engineer

Johns Hopkins Applied Physics Laboratory

Laurel, MD • On-site

$127K - $165K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 13 days ago

Johns Hopkins Applied Physics Laboratory rating

9.6

Company rating: 9.6 out of 10

Based on 8 frontline employees who took The Breakroom Quiz

2nd of 74 rated research

Job description

Description
Are you motivated to develop next-generation optical and optoelectronic devices that protect our nation and advance scientific discovery?
Do you thrive in a cleanroom setting, working with expert teams to build high precision, multilayer optics and develop groundbreaking electronic materials?
If so, we're looking for someone like you to join our team at APL.
We are seeking a Junior Electronic and Optical Materials Device Fabrication Engineer to help us fabricate world-class micro- and nanoscale devices. The role is predominantly fabrication-focused, with a vast majority of working hours spent in a cleanroom or laboratory environment, including the cleanroom at JHU-APL in Laurel, MD and other multi-user facilities within a 20 min to 1 hr drive. You will be joining a hardworking team of engineers and scientists who are passionate about developing ground-breaking solutions to solve the nation's critical challenges!
In this role, you'll...
  • Design and optimize multilayer layouts with Python scripting for layout generation and data analysis.
  • Develop advanced fabrication recipes for multilayer optics using e-beam lithography and direct-write lithography on various optical substrates.
  • Apply AI and machine-learning approaches to improve fabrication processes
  • Maintain version-controlled GDS/layout databases with Python-based automation for parametric layout generation, fracturing, and design rule checking, and develop data-analysis pipelines linking design, fabrication, and metrology data for CD, overlay, and yield trends.
  • Refine deposition techniques across systems such as e-beam, thermal, and sputter evaporators, PECVD, ALD, and MOCVD to enhance device quality.
  • Characterize thin films and processes using tools like SEM/EDS, XPS, XRD, AFM, ellipsometry, and film stress analysis to ensure quality and performance.
  • Execute precision etching processes to meet tight design specifications and tolerances.
  • Maintain and update process documentation, including runsheets, for accuracy and repeatability.
  • Collaborate with teams to innovate and improve fabrication workflows.

Qualifications
You meet our minimum qualifications for the job if you...
  • Have a Bachelor's Degree in Materials Science and Engineering, Physics, Electrical Engineering, or related field.
  • Have 2+ years of experience working in a microfabrication or nanofabrication cleanroom environment.
  • Are proficient in multilayer layout design and modification, with expertise in Python scripting for both design automation and data analysis.
  • Have experience optimizing etch and deposition processes, including thermal evaporation, e-beam, sputtering, PECVD, ICP RIE, and ion mill techniques.
  • Are willing and able to travel locally to shared cleanrooms and laboratory facilities
  • Are able to obtain Interim Secret level security clearance by your start date and can ultimately obtain Secret level clearance. If selected, you will be subject to a government security clearance investigation and must meet the requirements for access to classified information. Eligibility requirements include U.S. citizenship.

You'll go above and beyond our minimum requirements if you...
  • Have a Master's degree in Materials Science and Engineering, Physics, Electrical Engineering, or related field.
  • Are proficient in multilayer layout design and modification, with expertise in Python scripting for both design automation and data analysis.
  • Have experience using e-beam lithography to pattern meta-optic devices.
  • Have experience patterning materials for photonic integrated circuits, adaptive optics, RF, IR, MEMS, thermoelectric, or photovoltaic devices.
  • Familiarity with advanced characterization tools, including SEM/EDS, XPS, XRD, AFM, ellipsometry, and spectroscopic reflectometry.

About Us
Why Work at APL?
The Johns Hopkins University Applied Physics Laboratory (APL) brings world-class expertise to our nation's most critical defense, security, space and science challenges. While we are dedicated to solving complex challenges and pioneering new technologies, what makes us truly outstanding is our culture. We offer a vibrant, welcoming atmosphere where you can bring your authentic self to work, continue to grow, and build strong connections with inspiring teammates.
At APL, we celebrate our differences of perspectives and encourage creativity and bold, new ideas. Our employees enjoy generous benefits, including a robust education assistance program, unparalleled retirement contributions, and a healthy work/life balance. APL's campus is located in the Baltimore-Washington metro area. Learn more about our career opportunities at https://www.jhuapl.edu/careers.
All qualified applicants will receive consideration for employment without regard to race, creed, color, religion, sex, gender identity or expression, sexual orientation, national origin, age, physical or mental disability, genetic information, veteran status, occupation, marital or familial status, political opinion, personal appearance, or any other characteristic protected by applicable law. APL is committed to providing reasonable accommodation to individuals of all abilities, including those with disabilities. If you require a reasonable accommodation to participate in any part of the hiring process, please contact Accessibility@jhuapl.edu.
The referenced pay range is based on JHU APL's good faith belief at the time of posting. Actual compensation may vary based on factors such as geographic location, work experience, market conditions, education/training and skill level with consideration for internal parity. For salaried employees scheduled to work less than 40 hours per week, annual salary will be prorated based on the number of hours worked. APL may offer bonuses or other forms of compensation per internal policy and/or contractual designation. Additional compensation may be provided in the form of a sign-on bonus, relocation benefits, locality allowance or discretionary payments for exceptional performance. APL provides eligible staff with a comprehensive benefits package including retirement plans, paid time off, medical, dental, vision, life insurance, short-term disability, long-term disability, flexible spending accounts, education assistance, and training and development. Applications are accepted on a rolling basis.
Minimum Rate
$85,000 Annually
Maximum Rate
$195,000 Annually

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