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Internship Asic Rtl Design Engineer Jobs in Washington, DC

Next Step Systems

FPGA Engineer

Linthicum, MD · On-site

... partition design within ASIC/FPGA, create specification documents. - Develop RTL designs using ... and/or FPGAs (internship and research experience qualifies). - 2+ years of experience in ...

Next Step Systems

Senior FPGA Electrical Engineer

Linthicum, MD · On-site

$102K - $138K/yr

... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...

Next Step Systems

Senior FPGA Engineer

Linthicum, MD · On-site

$128K - $164K/yr

... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...

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Internship Asic Rtl Design Engineer information

See Washington, DC salary details

$106.5K

$170.1K

$228.8K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 4, 2026, the average yearly pay for internship asic rtl design engineer in Washington, DC is $170,111.00, according to ZipRecruiter salary data. Most workers in this role earn between $148,900.00 and $203,900.00 per year, depending on experience, location, and employer.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

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Internship Asic Rtl Design Engineer jobs near you

Senior ASIC Digital Design Engineer

General Dynamics Mission Systems, Inc

Annapolis Junction, MD

Full-time

Re-posted 22 days ago

General Dynamics Mission Systems rating

7.9

Company rating: 7.9 out of 10

Based on 30 frontline employees who took The Breakroom Quiz

127th of 241 rated software companies

Job description

Education Requirements:

Requires a Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree plus 3 years of job-related experience.  

Clearance Requirements:

Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.


We're looking for an Advanced ASIC Design Engineer with solid hands-on experience in RTL design and a foundational understanding of the full ASIC/FPGA design lifecycle. This is a technical role for someone who is ready to take on meaningful ownership of design tasks within a collaborative, high-performing team.

If your career has been primarily running P&R tools, this probably isn't the right fit. We also need someone who has moved beyond the "burn it and see if it works" model of FPGA development — on ASIC, you don't get that luxury. We need an RTL designer who understands that correctness has to be established through rigorous simulation, formal verification, and independent review long before anything gets near silicon.

The right candidate has worked in larger, structured design environments where verification is a discipline in its own right — with dedicated verification partners, formal review processes, and clear functional closure criteria. A self-starter who can work independently on assigned tasks, drives progress without constant direction, and brings a problem-solving mindset to everything they touch.

What You'll Do

  - Own RTL design tasks — Develop RTL with a focus on correctness: bus fabric integrity, clock domain crossings, reset order-of-operations, and design-for-verification

  - Contribute to timing closure — Work through synthesis, place and route, and static timing analysis; identify root causes of timing failures and contribute to fixes

  - Support verification efforts — Execute test and simulation plans in coordination with a dedicated verification team; understand and work within a formal verification process; verify results and help drive closure on failures

  - Participate in JIRA triage — Review incoming issues and help maintain an accurate and actionable backlog

  - Participate in code reviews — Engage in RTL code reviews, providing and receiving constructive technical feedback

  - Support program planning — Provide input on task status, schedule risk, and level of effort to support IMS and EV reporting

  - Support proposals — Contribute to basis of estimates (BOEs) for proposals, providing technical input on scope and level of effort for assigned design tasks

  - Support technology evaluation — Assist in assessing foundry technologies, device libraries, IP cores, and EDA tooling

  - Collaborate broadly — Participate in Integrated Product Teams and working groups

What We're Looking For

  - 5–8+ years of ASIC/FPGA design experience, with meaningful time spent as an RTL designer

  - Experience working in larger, structured design teams with formal verification processes and independent verification partners — not solely in small-team or solo development environments

  - Demonstrated understanding that design correctness is established through simulation, formal verification, and peer review — not through iteration on hardware

  - Some experience contributing to ASIC tape-out efforts is a plus

  - Familiarity with FinFET process nodes (7nm, 5nm, or similar) is a differentiator

  - Familiarity with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent)

  - Working knowledge of:

    - RTL design and microarchitecture

    - Bus fabric design and verification

    - Clock domain crossing (CDC) analysis

    - Reset sequencing and validation

    - Timing closure fundamentals

    - Power analysis basics

Skills & Knowledge

  - Solid understanding of ASIC/FPGA engineering concepts, RTL coding practices, and synthesis flows

  - Familiarity with industry-standard EDA tools (synthesis, simulation, formal verification, STA)

  - Ability to work independently on assigned tasks while coordinating effectively within the team

  - Familiarity with vendor and foundry capabilities

  - Proficiency in JIRA for issue tracking and backlog management

  - Proficiency in Microsoft Office for documentation and communication

Why This Role

You won't be handed a spec and told to code. You'll take real ownership of design tasks, with exposure across the full ASIC lifecycle and the opportunity to grow alongside experienced engineers. This is a role where your work matters, your initiative is recognized, and the team values engineers who take ownership and see problems through to resolution.


This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.
USD $142,166.00 - USD $150,000.00 /Yr.

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!


Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

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