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About Altera At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

As a Sr. Mixed Signal Design Engineer you will be part of a team designing various mixed‑signal circuit designs on Intel FPGAs such as voltage regulators, bandgaps and bias circuits, Analog to digital converter (ADC), Delay locked loops (DLLs), high speed clock distribution and other clocking circuits, high speed transmitters and receivers on advanced process nodes and have an opportunity to work on a diverse set of blocks and tasks in all phases of the design. The ideal candidate will be an independent self‑starter who can own/design a custom analog or digital IP. An important part of this role is delivering all aspects of the design and collateral, including timing and reliability collateral. You should be a motivated team‑player who is able to work with cross‑functional and cross‑geo teams to understand, articulate and solve problems.

• Technical path‑finding, innovation, micro‑architecture and design of analog/mixed‑signal circuits including regulators and bandgaps to meet architectural specifications in advanced process nodes.
• Contribute to architectural trade‑off studies and design methodology improvements.
• Design, develop and deliver circuit building block schematic, perform pre‑layout and post‑layout design optimization to meet design specification across PVT, process variation sensitivity analysis, aging, EOS, RV checks for design reliability.
• Work with custom layout team to define plan (floorplan, routing, matching, metal grid etc) to meet circuit performance.
• Collateral generation like circuit Integration spec, BMOD, timing model, power model, ICCT, IBIS, alpha numbers.
• Own specifications and design verification plans covering functionality, performance and reliability meeting high volume productization requirement.
• Collaborate with logic designer, logic verification designer, structural physical design engineers, integration engineers, signal integrity and power deliver engineer to define clear collateral handoff requirements to ensure efficient IP integration.
• Perform post silicon data analysis and debug and make necessary design enhancement to meet design specification.
• Conduct design reviews; actively contribute to design reviews.
• Represent the team on related IP in cross‑functional meetings and co‑ordination of deliverables.
• Work with external IP vendors as point of contact for analog designs.

• Good communication and presentation skills to enable cross functional collaboration.
• Effective prioritization and time management skills.
• Willing to work in a dynamically changing, cross geographical, cross functional environment.
• Attention to detail to ensure quality and ingenuity and drive to solve issues.
• Be a team player and willing to work autonomously and also collaboratively/flexibility in a team environment.
• Be a mentor and willing to guide/train upcoming engineers.

Salary: $149,100 - $215,925 USD.

• BSEE/MSEE/PhD in Electrical Engineering or equivalent with a minimum of 10 years of experience in analog/mixed signal, high speed, or high voltage IO designs.
• 10+ years of experience in design of analog and mixed signal circuits like amplifiers, comparators, regulators, ADC, high speed transmitters and receivers (SerDes, PAM‑4, PCIe, DDR, etc.).
• Exposure to analog/mixed signal circuit design and layout flow and running post‑layout simulations.
• Solid understanding of analog design trade‑offs and design for process variation and reliability in modern CMOS technologies.
• Proficient in circuit design tools like Virtuoso, Spice, StarRC, Totem etc.
• Understanding of Verilog, static timing analysis, UPF and related aspects of mixed signal design.

• Experience with high‑speed receivers.

• Job Type: Regular
• Shift: Shift 1 (United States of America)
• Primary Location: San Jose, California, United States

We use artificial intelligence to screen, assess, or select applicants for the position.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Altera provides leadership programmable solutions that are easy‑to‑use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end‑to‑end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.