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Dv Engineer Jobs (NOW HIRING)

Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation ...

Senior DV Engineer

Saratoga, CA · On-site

$120K - $220K/yr

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

Senior DV Engineer

Saratoga, CA · On-site

$120 - $220/hr

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

Senior DV Engineer

Saratoga, CA · On-site

$120K - $220K/yr

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

Staff DV Engineer

Saratoga, CA · On-site

$120K - $220K/yr

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

Principal DV Engineer

Saratoga, CA · On-site

$120K - $220K/yr

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

Principal DV Engineer

Saratoga, CA · On-site

$120K - $220K/yr

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

Senior ASIC DV Engineer

San Jose, CA · On-site

$141.30 - $226/hr

Debug RTL and gate simulations and work with design engineers to verify fixes. * Write diagnostics for validation of FPGA prototypes (pre‑tapeout) and ASIC. * Replicate silicon bugs in simulation ...

We are searching for a hard-working engineer to join our exciting team of problem solvers. Description In this highly transparent and interactive role, your primary responsibilities will include ...

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Dv Engineer information

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$53

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How much do dv engineer jobs pay per hour?

As of Aug 15, 2026, the average hourly pay for dv engineer in the United States is $53.63, according to ZipRecruiter salary data. Most workers in this role earn between $43.27 and $62.26 per hour, depending on experience, location, and employer.

What cities are hiring for Dv Engineer jobs?

Cities with the most Dv Engineer job openings:

What states have the most Dv Engineer jobs?

States with the most job openings for Dv Engineer jobs include:

Infographic showing various Dv Engineer job openings in the United States as of August 2026, with employment types broken down into 92% Full Time, 2% Part Time, and 6% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $111,552 per year, or $53.6 per hour.

SoC Design Verification Engineer

SWITS DIGITAL Private Limited

San Jose, CA • On-site

$159K - $194K/yr

Full-time

Re-posted 14 days ago


Job description

Job Title: SoC Design Verification Engineer
Location: San Jose, CA
Job Description:
We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex SoCs. The role involves working closely with architecture, design, and software teams to ensure silicon meets performance, power, and functionality targets.
Key Responsibilities:
  • Develop and execute SoC-level validation and performance verification strategy
  • Build system-level testbenches, workloads, and performance models
  • Analyze performance bottlenecks across CPU, memory, interconnect, and accelerators
  • Perform power and performance trade-off analysis
  • Collaborate with architecture, RTL, and software teams
  • Debug issues at system level (HW + FW/SW interaction)

Required Skills:
  • Strong experience in SoC-level DV / Performance validation
  • Understanding of CPU architecture, memory hierarchy, NoC/interconnect
  • Expertise in SystemVerilog/UVM + C/C++/Python
  • Experience with performance profiling tools
  • Strong debugging and analytical skills

Good to Have:
Experience in post-silicon validation / bring-up
Knowledge of AI/ML or high-performance computing workloads