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Dv Engineer Jobs in California (NOW HIRING)

DV engineer

San Jose, CA · On-site

$75 - $90/hr

Senior DV Engineer Who We Are: Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies ...

New

Senior DV Engineer Location - San Jose, CA Contract :12+ months Experience: 10+ years The Senior Engineer - DV is responsible for leading and executing end-to-end design verification activities for ...

New

DV engineer

San Jose, CA · On-site

$75 - $90/hr

Senior DV Engineer Who We Are: Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies ...

New

Senior DV Engineer Who We Are: Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies ...

New

Senior DV Engineer Location - San Jose, CA, USA Contract :12+ months Experience: 10+ years The Senior Engineer - DV is responsible for leading and executing end-to-end design verification activities ...

Senior DV Engineer

San Jose, CA · On-site

$160K - $190K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Senior DV Engineer Who We Are: Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies ...

Senior ASIC/SoC Design Verification Engineer (Chip-Level Verification) An outstanding, full-time opening is available in Silicon Valley, CA for an experienced ASIC/SoC Design Verification Engineer ...

GPU DV Engineer

Santa Clara, CA · On-site

$182K - $273K/yr

Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation ...

Senior DV Engineer

Saratoga, CA · On-site

$120K - $220K/yr

  • Medical

  • PTO

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

Principal DV Engineer

Saratoga, CA · On-site

$120 - $220/hr

  • Medical

  • PTO

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

Staff DV Engineer

Saratoga, CA · On-site

$120K - $220K/yr

  • Medical

  • PTO

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation ...

Senior DV Engineer

Saratoga, CA · On-site

$120K - $220K/yr

  • Medical

  • PTO

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

Senior DV Engineer

Saratoga, CA · On-site

$120 - $220/hr

  • Medical

  • PTO

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

Principal DV Engineer

Saratoga, CA · On-site

$120K - $220K/yr

  • Medical

  • PTO

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We ...

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Showing results 1-20

Dv Engineer information

See California salary details

$25

$52

$75

How much do dv engineer jobs pay per hour?

As of Aug 14, 2026, the average hourly pay for dv engineer in California is $52.93, according to ZipRecruiter salary data. Most workers in this role earn between $42.69 and $61.44 per hour, depending on experience, location, and employer.

What cities in California are hiring for Dv Engineer jobs?

Cities in California with the most Dv Engineer job openings:

Infographic showing various Dv Engineer job openings in California as of August 2026, with employment types broken down into 88% Full Time, 5% Part Time, 2% Temporary, and 5% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $110,091 per year, or $52.9 per hour.

$75 - $90/hr

Full-time

Posted 2 days ago

New


Quest Global rating

7.8

Company rating: 7.8 out of 10

Based on 11 frontline employees who took The Breakroom Quiz

242nd of 447 rated engineering


Job description

Job Requirements
POSITION: Senior DV Engineer
Who We Are:
Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries.
We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we're eager to hear from you. The achievers and courageous challenge-crushers we seek, have the following characteristics and skillsRole Summary
The Senior Engineer - DV is responsible for leading and executing end-to-end design verification activities for IP, Subsystem, or SoC-level projects. This role involves technical ownership and close collaboration with design, architecture, and customer teams to achieve verification closure with high quality.
Key Responsibilities
Design Verification of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc.
• Strong in HVL (UVM / SystemVerilog / OVM), C/C++, Perl, TCL programming/scripting skills, verification methodologies and flows.
• Strong in constraint random verification, assertion writing, coverage analysis, debugging.
• Familiarity with ARM cores, formal verification, SV DPI-C is a plus.
• Experience with AMS/Low Power verification techniques and verifying mixed signal ICs a plus.
• Good knowledge of EDA tools. Experience with signal processing and FPGA based prototyping a plus.
• Must be a team player with good oral and written communication skills.
• Self-motivated with the ability to work independently and interface effectively with engineers across divisions and remote locations
Education
BE / BTech / MTech in Electronics, Electrical, or related disciplines.
Work Experience
This role is considered Onsite for San Jose, California.
  • You must be able to commute to and from the location with your own transportation arrangements to meet the required working hours.
  • Pay range : $75 - $90 per hour

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