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Dv Engineer Jobs in Riverside, CA (NOW HIRING)

Senior ASIC DV Engineer

Irvine, CA · On-site

$141K - $226K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

As a verification engineer, your responsibilities will include: * Architecting block and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded ...

Design Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and verifying in any of the following key ...

Design Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and verifying in any of the following key ...

Wireless SOC Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Wireless SOC Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Wireless SOC Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Wireless SOC Verification Engineer

Irvine, CA

$122K - $214K/yr

  • Medical

  • Dental

  • Retirement

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Wireless SOC Verification Engineer

Irvine, CA

$122K - $214K/yr

  • Medical

  • Dental

  • Retirement

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Wireless SOC Verification Engineer

Irvine, CA

$122K - $214K/yr

  • Medical

  • Dental

  • Retirement

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...

Wireless SOC Verification Engineer

Irvine, CA

$175K - $308K/yr

  • Medical

  • Dental

  • Retirement

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Wireless SOC Verification Engineer

Irvine, CA

$175K - $308K/yr

  • Medical

  • Dental

  • Retirement

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Wireless SOC Verification Engineer

Irvine, CA

$175K - $308K/yr

  • Medical

  • Dental

  • Retirement

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Sr. Mechanical/Electrical Engineer

Lake Forest, CA · On-site

$114K - $148K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

Support PPAP, DV/PV testing, launch readiness, and ongoing quality improvement initiatives ... Serve as the engineering subject matter expert for fuelsystemand electromechanical product ...

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Showing results 1-20

Dv Engineer information

See Riverside, CA salary details

$26

$55

$80

How much do dv engineer jobs pay per hour?

As of Aug 14, 2026, the average hourly pay for dv engineer in Riverside, CA is $55.95, according to ZipRecruiter salary data. Most workers in this role earn between $45.14 and $64.95 per hour, depending on experience, location, and employer.

What cities near Riverside, CA are hiring for Dv Engineer jobs?

Cities near Riverside, CA with the most Dv Engineer job openings:

Infographic showing various Dv Engineer job openings in Riverside, CA as of August 2026, with employment types broken down into 92% Full Time, 2% Part Time, and 6% Contract. Highlights an 87% Physical, 4% Hybrid, and 9% Remote job distribution, with an average salary of $116,379 per year, or $56 per hour.

Senior ASIC DV Engineer

Broadcom

Irvine, CA • On-site

$141K - $226K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 28 days ago


Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

19th of 157 rated electronics manufacturers


Job description

Please Note:

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Job Description:

You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include:

  • Architecting block and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces.

  • Using your thorough knowledge of mixed-signal simulations (AMS, Spice,etc), developing test plans and coverage metrics from specifications and writing block and chip-level tests.

  • Debugging RTL and Gate simulations and work with design engineers to verify fixes.

  • Writing diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.

  • Replicating silicon bugs in simulation environments and validating fixes or SW workarounds.

  • Converting verification tests to test patterns and assisting Test Engineers on ATE vector bring up.

  • Evaluating latest verification methodologies and developing scripts etc. to automate verification flows.

  • Experience understanding and verifying low power silicon for mobile applications with good knowledge of UPF low power verification flow

  • Ability to take customer requirements to verify full chip design and architecture

Qualifications:

  • Bachelors in Engineering and 12+ years of related experience; or Masters degree in Engineering and 10+ years of related experience; or PhD in Engineering and 7+ years of related experience

  • MS or PhD is preferred

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is$141,300 - $226,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.


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