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Dv Engineer Jobs in Riverside, CA (NOW HIRING)

Insilico

Design Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and verifying in any of the following key ...

Insilico

Design Verification Engineer

Irvine, CA

$146K - $178K/yr

Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and verifying in any of the following key ...

Apple

Wireless SOC Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Apple

Wireless SOC Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Apple

Wireless SOC Verification Engineer

Irvine, CA

$122K - $214K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Apple

Wireless SOC Verification Engineer

Irvine, CA · On-site

$122K - $214K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Apple

Wireless SOC Verification Engineer

Irvine, CA · On-site

$122K - $214K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Apple

Wireless SOC Verification Engineer

Irvine, CA · On-site

$175K - $308K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Apple

Wireless SOC Verification Engineer

Irvine, CA · On-site

$175K - $308K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Apple

Wireless SOC Verification Engineer

Irvine, CA · On-site

$175K - $308K/yr

Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Apple

PHY RTL Design Engineer

Irvine, CA · On-site

... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...

Marmon

Sr. Mechanical/Electrical Engineer

Lake Forest, CA · On-site

$114K - $148K/yr

Support PPAP, DV/PV testing, launch readiness, and ongoing quality improvement initiatives ... Serve as the engineering subject matter expert for fuelsystemand electromechanical product ...

Relief Cardiovascular

R&D Engineer II

Anaheim, CA · On-site

$85K - $110K/yr

You will create drawings, support tolerance stack-ups, build devices and DV fixtures, execute ... S. in Biomedical Engineering or Mechanical Engineering or a closely related discipline. • 2-4 ...

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All JobsDv Engineer JobsDv Engineer Jobs in Riverside, CA

Dv Engineer information

See Riverside, CA salary details

$26

$55

$80

How much do dv engineer jobs pay per hour?

As of Sep 4, 2026, the average hourly pay for dv engineer in Riverside, CA is $55.95, according to ZipRecruiter salary data. Most workers in this role earn between $45.14 and $64.95 per hour, depending on experience, location, and employer.

What cities near Riverside, CA are hiring for Dv Engineer jobs?

Cities near Riverside, CA with the most Dv Engineer job openings:

Dv Engineer jobs near you
Infographic showing various Dv Engineer job openings in Riverside, CA as of August 2026, with employment types broken down into 88% Full Time, 8% Part Time, and 4% Contract. Highlights an 85% Physical, 5% Hybrid, and 10% Remote job distribution, with an average salary of $116,379 per year, or $56 per hour.

Design Verification Engineer

Insilico

Irvine, CA • On-site

$146K - $178K/yr

Contractor

Re-posted 14 days ago

Job description

Company Description
Insilico is an End-to-End specialized VLSI, Embedded Design & Software services and solutions company. It operates in the "Compute" & "Connectivity" space.
Insilico is founded by industry veterans, who are strong leaders and practitioners with diverse experience in all the relevant aspects of technology and execution. The management and its entire team, handpicked from among the best talents in the industry, can adapt to the evolving technologies and growing market challenges internationally. Insilico has very flexible business models to suit a plethora of client needs.
With a current clientele of top semiconductor companies, Insilico has a wide and diversified spectrum of service offerings in expansive domains within the ambit of Embedded Design & Software, and in almost all areas of VLSI design, from Spec-to-Silicon, on a wide range of ASICs & CPUs/GPUs in all the latest technologies, including 7nm.
Being an integral part of a larger business eco-system, Insilico has the foundation of strong financials, validated processes, robust infrastructure and a global network of reputable clientele.
Insilico's service portfolio caters to products that empower the world of Communication, Networking, CPU/Servers, Automobile, Bio-Medicals, Consumer Electronics and a wide range of IOTs.
Headquartered in the US, it has operations in India & APAC.
Job Description
Job Title: Design Verification Engineer
Location: Santa Clara, CA
Duration: 06 months (High Possibility of an extension)
Job Description:
Senior DV engineer responsible for defining and implementing verification methodology and verifying in any of the following key areas of our next generation ASIC:
1. PCIE verification background
2. 400G MAC verification background
Qualifications
Additional Information
All your information will be kept confidential according to EEO guidelines.

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