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Dv Engineer Jobs in Massachusetts (NOW HIRING)

Manager, Technical Operations, DV+ Broomfield, CO New York City, NY Boston, MA Hybrid Schedule (M/F ... Partner directly with Product, Engineering, and Account Management leadership to shape initiatives ...

Senior Test Engineer Key Skills: Embedded Systems Testing, Mobile Testing, Defect Management, Risk ... Responsible for coordinating Design Verification (DV) activities between client stakeholders and ...

Collaborate with architects, DV engineers, digital designers, and analog/photonics designers to define validation flows. * Create reusable and scalable test bench components that enable efficient and ...

PHY Design Verification Engineer

Waltham, MA · On-site

$184.70 - $324.80/hr

You will interact with DV methodologists, designers, and communication systems engineers to develop reusable test bench and verification environment deploying the latest methodology with ...

Senior Data Engineer

Boston, MA · On-site +1

$115K - $156K/yr

Data Engineer & Senior Data Engineer Location: Remote or Boston, MA & San Mateo, CA Duration: FTE ... Idealcandidate will be strong in SQL, python, tableau, Qlik or another cloud DV tooland mid (Boston ...

Design Verification Engineer

Waltham, MA · On-site

$146K - $179K/yr

Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a ... programming skills with knowledge of data structures and algorithms Experience with Python, Perl ...

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Dv Engineer information

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How much do dv engineer jobs pay per hour?

As of Aug 14, 2026, the average hourly pay for dv engineer in Massachusetts is $58.57, according to ZipRecruiter salary data. Most workers in this role earn between $47.26 and $67.98 per hour, depending on experience, location, and employer.

What cities in Massachusetts are hiring for Dv Engineer jobs?

Cities in Massachusetts with the most Dv Engineer job openings:

Infographic showing various Dv Engineer job openings in Massachusetts as of August 2026, with employment types broken down into 92% Full Time, 3% Part Time, and 5% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $121,829 per year, or $58.6 per hour.

Staff/Sr. Staff Design Verification

Lightmatter

Boston, MA • On-site

Full-time

Re-posted 27 days ago


Job description

As a Design Verification Engineer at Lightmatter, you will find yourself at the heart of a dynamic, interdisciplinary team. Your role will involve close collaboration with our digital design experts, using UVM testbench techniques to rigorously verify their designs. Your responsibilities will include working alongside photonic and analog designers, gaining a deep understanding of their innovative designs, and applying Real Number Modeling (RNM) and AMS verification methods. This critical function ensures the integrity of their work. We are hiring at multiple levels. 

Your interaction with the Architecture team will be crucial in comprehending system requirements and spearheading performance verification. This role offers a unique platform to enhance your skills across a spectrum of areas including UVM, AMS modeling, mixed-signal verification, post-silicon validation formal verification, emulation, and both performance modeling and verification.

Responsibilities

  • Define and enhance the DV methodologies required for integrated digital, analog, and photonic devices with a strong emphasis on emulation for design verification.
  • Create and execute test plans to ensure high-quality tapeouts that meet functional and performance goals, while leveraging emulation where appropriate.
  • Collaborate with architects, DV engineers, digital designers, and analog/photonics designers to define validation flows.
  • Create reusable and scalable test bench components that enable efficient and effective verification.
  • Close coverage and finish all DV signoff requirements, with a focus on leveraging mixed signal simulations to achieve high coverage metrics
  • Work on block level and full chip design verification.
  • Integrate analog design IPs from vendors and internal teams and develop verification environments for simulation and emulation.
  • Work with analog design engineers to create behavioral models for analog designs and with digital design engineers to integrate models/testcase/checkers into upper levels

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience
  • Minimum of 8 years of design verification and SystemVerilog experience
  • 2+ years of experience in Python
  • Expertise in developing with the UVM library
  • Experience with simulators such as Xcelium, ModelSim, Questa, or VCS
  • Strong problem solver and collaborator

Preferred Qualifications 

  • Master's degree or higher in Electrical Engineering, Computer Engineering, a related field, or equivalent experience with 6 years of relevant experience 
  • Experience with post-silicon validation and debug
  • Experience with AMS verification

This role is open to multiple levels. Education, years of experience, and interview performance will be the determining factor for leveling.

Staff: $186,000 - $218,000

Sr Staff: $206,000 - $236,000