Job Title: 3D Stacked Logic Design Engineer Office Location: San Jose, CA Job Type: Full-Time Work ... To strengthen leadership in the DRAM-on-Logic era through optimized DRAM die design, we are seeking ...
Job Title: 3D Stacked Logic Design Engineer Office Location: San Jose, CA Job Type: Full-Time Work ... To strengthen leadership in the DRAM-on-Logic era through optimized DRAM die design, we are seeking ...
Bachelor's Degree in Electrical Engineering or Computer Science or related discipline with 10+ ... DRAM or other high performance memory IC design, application, test, or product engineering
New
Bachelor's Degree in Electrical Engineering or Computer Science or related discipline with 10+ ... DRAM or other high performance memory IC design, application, test, or product engineering
New
Manager, DRAM Customer Quality
San Jose, CA · On-site
$163 - $253/hr
We are looking for a technical, customer‑focused engineer with skills and/or interests in ... DRAM or other high performance memory IC design, application, test, or product engineering
Posted today
Manager, DRAM Customer Quality
San Jose, CA · On-site
$163 - $253/hr
We are looking for a technical, customer‑focused engineer with skills and/or interests in ... DRAM or other high performance memory IC design, application, test, or product engineering
Posted today
Principal DRAM Product Applications Engineer San Jose, California, United States of America
San Jose, CA · On-site
$177 - $302/hr
In this role, you'll be the technical connection between customers and engineering for our DRAM portfolio, including HBM, DDR, and GDDR. You'll guide product validation, improve quality, and help ...
Principal DRAM Product Applications Engineer San Jose, California, United States of America
San Jose, CA · On-site
$177 - $302/hr
In this role, you'll be the technical connection between customers and engineering for our DRAM portfolio, including HBM, DDR, and GDDR. You'll guide product validation, improve quality, and help ...
3D Stacked Logic Design Engineer
San Jose, CA · On-site
$150K - $320K/yr
As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory ... Onsite Job Title: 3D Stacked Logic Design Engineer Office Location: San Jose, CA Job Type ...
3D Stacked Logic Design Engineer
San Jose, CA · On-site
$150K - $320K/yr
As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory ... Onsite Job Title: 3D Stacked Logic Design Engineer Office Location: San Jose, CA Job Type ...
Bachelor's Degree in Electrical Engineering or Computer Science or related discipline with 10+ ... DRAM or other high performance memory IC design, application, test, or product engineering
New
Quick apply
Bachelor's Degree in Electrical Engineering or Computer Science or related discipline with 10+ ... DRAM or other high performance memory IC design, application, test, or product engineering
New
Sr. Failure Analysis Engineer
Newark, CA · On-site
$117K - $161K/yr
Overview We are seeking a seasoned and highly skilled Senior DRAM Failure Analysis Engineer with extensive expertise in high-speed, high-capacity DRAM modules. The ideal candidate will have 5+ years ...
Sr. Failure Analysis Engineer
Newark, CA · On-site
$117K - $161K/yr
Overview We are seeking a seasoned and highly skilled Senior DRAM Failure Analysis Engineer with extensive expertise in high-speed, high-capacity DRAM modules. The ideal candidate will have 5+ years ...
Understanding of qualification of HBM/DRAM, and of the failure analysis procedure. * Willingness to travel and to build positive relationships with customers as needed. Preferred Qualifications:
Understanding of qualification of HBM/DRAM, and of the failure analysis procedure. * Willingness to travel and to build positive relationships with customers as needed. Preferred Qualifications:
AI-Driven DRAM Architect & Systems Strategist (Folsom)
Folsom, CA · On-site
$135K/yr
Micron Technology is seeking a Product Architecture Engineer for DRAM based in Folsom, California. This position involves defining how Micron memory technologies support AI training and inference ...
AI-Driven DRAM Architect & Systems Strategist (Folsom)
Folsom, CA · On-site
$135K/yr
Micron Technology is seeking a Product Architecture Engineer for DRAM based in Folsom, California. This position involves defining how Micron memory technologies support AI training and inference ...
Firmware Engineer
Rancho Cordova, CA · On-site
$170K/yr
Senior Firmware Engineer (BE) Salary: $ 180,000.00/Year | Full-Time | Rancho Cordova, CA We have ... DRAM Bring-Up and Stability Verification * Configure memory controller parameters, timing settings ...
Quick apply
Firmware Engineer
Rancho Cordova, CA · On-site
$170K/yr
Senior Firmware Engineer (BE) Salary: $ 180,000.00/Year | Full-Time | Rancho Cordova, CA We have ... DRAM Bring-Up and Stability Verification * Configure memory controller parameters, timing settings ...
On/Off-Chip SI/PI Engineer
San Jose, CA · On-site
$47.25 - $54/hr
On/Off-Chip SI/PI Engineer Office Location: San Jose, CA Job Type: Full-Time Work Model: Onsite Job ... Drive system-level co-optimization beyond standalone DRAM design. * Build deep technical ...
On/Off-Chip SI/PI Engineer
San Jose, CA · On-site
$47.25 - $54/hr
On/Off-Chip SI/PI Engineer Office Location: San Jose, CA Job Type: Full-Time Work Model: Onsite Job ... Drive system-level co-optimization beyond standalone DRAM design. * Build deep technical ...
We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next ... BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education ...
We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next ... BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education ...
Sr. Failure Analysis Engineer
Newark, CA · On-site
$117K - $161K/yr
Overview We are seeking a seasoned and highly skilled Senior DRAM Failure Analysis Engineer with extensive expertise in high-speed, high-capacity DRAM modules. The ideal candidate will have 5+ years ...
Sr. Failure Analysis Engineer
Newark, CA · On-site
$117K - $161K/yr
Overview We are seeking a seasoned and highly skilled Senior DRAM Failure Analysis Engineer with extensive expertise in high-speed, high-capacity DRAM modules. The ideal candidate will have 5+ years ...
Staff Field Applications Engineer-Data Center DRAM San Jose, California, United States of America
San Jose, CA · On-site
$142 - $242/hr
As a Datacenter DRAM Customer Engineer, you'll act as a primary technical advisor, helping customers design, qualify, and deploy memory solutions that power next-generation compute platforms. You'll ...
Staff Field Applications Engineer-Data Center DRAM San Jose, California, United States of America
San Jose, CA · On-site
$142 - $242/hr
As a Datacenter DRAM Customer Engineer, you'll act as a primary technical advisor, helping customers design, qualify, and deploy memory solutions that power next-generation compute platforms. You'll ...
We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next ... BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education ...
We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next ... BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education ...
Senior SE-MEM Engineer
Santa Clara, CA · On-site
$122K - $168K/yr
Applying your engineering knowledge of DRAM Testing and working with DRAM circuit and physical build. Candidates with HBM experience will have a distinct advantage. * Contributing to datacenter ATE ...
Senior SE-MEM Engineer
Santa Clara, CA · On-site
$122K - $168K/yr
Applying your engineering knowledge of DRAM Testing and working with DRAM circuit and physical build. Candidates with HBM experience will have a distinct advantage. * Contributing to datacenter ATE ...
Staff Engineer, SoC Architecture - Memory Subsystem and Interconnect
Mountain View, CA · On-site
$179.20 - $246.15/hr
Staff Engineer, SoC Architecture - Memory Subsystem and Interconnect Mountain View, CA Job Category ... Position Summary We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to ...
Staff Engineer, SoC Architecture - Memory Subsystem and Interconnect
Mountain View, CA · On-site
$179.20 - $246.15/hr
Staff Engineer, SoC Architecture - Memory Subsystem and Interconnect Mountain View, CA Job Category ... Position Summary We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to ...
Technical Marketing Engineer
San Jose, CA · On-site
DRAM design, testing, system validation, or application engineering experience. * Excellent ... communication, collaboration, coaching, negotiation, and presentation skills. * Strong knowledge of ...
Technical Marketing Engineer
San Jose, CA · On-site
DRAM design, testing, system validation, or application engineering experience. * Excellent ... communication, collaboration, coaching, negotiation, and presentation skills. * Strong knowledge of ...
Staff Engineer, Memory Systems Architecture
San Jose, CA · On-site
$163 - $253/hr
Staff Engineer, Memory Systems Architecture San Jose, California, United States Samsung ... The conventional DRAM failure analysis was physical electrical FA and physical FA. But, in the era ...
Staff Engineer, Memory Systems Architecture
San Jose, CA · On-site
$163 - $253/hr
Staff Engineer, Memory Systems Architecture San Jose, California, United States Samsung ... The conventional DRAM failure analysis was physical electrical FA and physical FA. But, in the era ...
Senior SE-MEM Engineer
$122K - $168K/yr
Applying your engineering knowledge of DRAM Testing and working with DRAM circuit and physical build. Candidates with HBM experience will have a distinct advantage. Contributing to datacenter ATE and ...
Senior SE-MEM Engineer
$122K - $168K/yr
Applying your engineering knowledge of DRAM Testing and working with DRAM circuit and physical build. Candidates with HBM experience will have a distinct advantage. Contributing to datacenter ATE and ...
Dram Engineer information
What is a DRAM engineer?
How does a DRAM engineer typically collaborate with cross-functional teams during the memory development process?
What are the key skills and qualifications needed to thrive as a DRAM engineer, and why are they important?
What is the difference between Dram Engineer vs Memory Engineer?
| Aspect | Dram Engineer | Memory Engineer |
|---|---|---|
| Credentials | Bachelor's or higher in Electrical Engineering, Computer Engineering, or related fields; certifications like IEEE are common | Similar educational background; often holds certifications in memory design or semiconductor manufacturing |
| Work Environment | Design labs, semiconductor fabs, R&D centers | Design labs, semiconductor manufacturing facilities, R&D centers |
| Industry Usage | Memory chip companies, electronics manufacturers | Memory chip companies, electronics manufacturers |
| Job Focus | Design and optimize DRAM modules, ensure performance and reliability | Design and develop various types of memory, including DRAM, SRAM, Flash |
Both Dram Engineers and Memory Engineers work in similar environments and industries, often sharing educational backgrounds and certifications. While Dram Engineers focus specifically on DRAM technology, Memory Engineers may work on a broader range of memory types. The roles are closely related, with overlapping skills in semiconductor design and testing.
What are popular job titles related to Dram Engineer jobs in California?
For Dram Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Dram Engineer jobs in California look for?
The top searched job categories for Dram Engineer jobs in California are:
What cities in California are hiring for Dram Engineer jobs?
Cities in California with the most Dram Engineer job openings:

Full-time
Medical, Retirement, PTO
Re-posted 21 days ago
Job description
Job Title: 3D Stacked Logic Design Engineer
Office Location: San Jose, CA
Job Type: Full-Time
Work Model: Onsite
Job Summary:
To strengthen leadership in the DRAM-on-Logic era through optimized DRAM die design, we are seeking talent capable of driving the co-design of 3D-stacked DRAM logic dies in close collaboration with U.S.-based customers. This strategic hiring initiative aims to enhance our global competitiveness by fostering deep engagement with key American clients, ensuring that our die design solutions are precisely aligned with their evolving technical requirements and market demands.
Responsibilities:
- Strengthen leadership in the DRAM-on-Logic era through advanced digital IP design for 3D-stacked DRAM.
- Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations for customers.
- Co-design 3D-stacked DRAM Logic Dies with U.S.-based customers.
- Improve competitiveness through close engagement with customers in the U.S.
- Design high-speed digital IP for 3D-stacked DRAM peripheral circuits and DRAM DFT with U.S.-based customers, covering RTL design to implementation.
- Conduct foundry verification of service-ready IPs and setting up infrastructure for the IP business.
- Deliver services to ensure seamless IP integration in customer design environments.
- Design digital logic blocks for 3D-stacked DRAM peripherals and Design-for-Test (DFT) features.
- Establish close technical engagement with key U.S.-based customers to address immediate 3D-stacked DRAM requirements.
- Establish close technical engagement with foundry partners (e.g., TSMC, Intel) to build digital IP for 3D-stacked DRAM.
Qualifications:
- Bachelor's degree or higher in Electrical Engineering or a related discipline with 5+ years of relevant experience.
- Development of Digital Logic IP/SoC based on Hardware Description Languages (Verilog, VHDL).
- Experience in RTL design and implementation memory PHY, hard macro IP for high-speed circuit, or high-speed digital IP design.
- Experience with memory controllers.
- Experience in memory Built-in Self-Test (BIST), DRAM Design for Test (DFT) / Design for Debug (DFD).
- Deep understanding of PPA analysis and optimization, and physical design.
- Excellent verbal and written communication in English; ability to present technical concepts to cross functional teams and senior management.
Benefits:
- Top Tier health insurance at no employee cost
- Paid day offs: Paid Time Off, Company Holidays, Parental Leave, Happy Fridays
- 401k Matching
- Flexible Spending Account (FSA) for Health Care & Dependent Care
- Educational reimbursement up to $10,000 per year
- Donation Matching and volunteering opportunities
- Corporate discount programs
- Free Breakfast/Lunch/Dinner provided to employees
About SK Hynix America
Sourced by ZipRecruiter
Industry
Semiconductor and electronic component manufacturing
Company size
201 - 500 Employees
Headquarters location
San Jose, CA, US
Year founded
1983