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As of Sep 14, 2026, the average yearly pay for director high performance in the United States is $119,323.00, according to ZipRecruiter salary data. Most workers in this role earn between $93,500.00 and $147,500.00 per year, depending on experience, location, and employer.

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Infographic showing various Director High Performance job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 82% Full Time, 15% Part Time, and 2% Contract. Highlights an 86% Physical, 1% Hybrid, and 13% Remote job distribution, with an average salary of $119,323 per year, or $57.4 per hour.

High Performance Compute Responsible Engineer

Long Beach, CA • On-site

Relativity Space
Aerospace Product and Parts Manufacturing • 501 - 1,000 employees
Learn more about Relativity Spaceexternal

Full-time

Re-posted 7 days ago

Key responsibilities

  • Design and validate high-speed digital compute boards, including schematic capture, component selection, and board-level validation.

  • Own the hardware from architecture through bring-up, diagnosing and resolving issues collaboratively with software engineers.

  • Architect and implement power delivery networks, thermal interfaces, and high-speed memory and interconnects for high-performance compute hardware.

Relativity Space rating

9.7

Company rating: 9.7 out of 10

Based on 8 frontline employees who took The Breakroom Quiz

Job description

About the Team: 

The Interplanetary Sciences Program was established to expand access to scientific exploration across our solar system. Its mission is to make planetary research faster, more affordable, and more capable than ever before by rethinking how science missions are designed, built, and operated. The program aims to enable scientists to send instruments to distant worlds without decades of development or prohibitive costs. By creating a sustainable model for interplanetary exploration, we are transforming space science from an occasional event into a continuous process of discovery that accelerates knowledge, broadens participation, and inspires the next generation of explorers.

About the Role:

You'll own the compute hardware from architecture through bring up - there's no hand-off to another team mid-stream. You pick the components, you design the board, you're the one powering it on and debugging it with the software team

  • Design the compute boards that deliver 10 TFLOPS of processing power for onboard AI/ML inference and science data processing within the Relay Data Center, owning the hardware from schematic capture through board-level validation
  • Architect and implement power delivery networks for high-complexity carrier boards, including 500W+ multi-rail designs with tight sequencing integrating GPU or CPU compute modules onto custom PCBs with high-speed coherent interconnects
  • Define thermal interface requirements (power dissipation budgets, junction temperature limits, interface material selection) and hand off specifications to the mechanical team, who own the thermal and packaging solution
  • Design and validate high-speed memory interfaces (HBM, DDR5), PCIe Gen 4/5 chip-to-chip links, and 10 GbE+ Ethernet connections to the payload network, along with board-level power monitoring, current limiting, and radiation upset recovery circuitry
  • Lead hardware bringup and board-level validation. Diagnose and resolve issues hands-on while collaborating closely with the software engineers who are building the software environment on top of your hardware

About You:

  • BSEE with 5+ years designing and bringing up high-speed digital compute boards, ideally with direct exposure to GPU, HPC, or modern accelerator platforms
  • Proficient in high-speed digital PCB design principles: multi-GHz signaling, dense BGA escape routing on high layer count stackups, and signal integrity analysis through both simulation and measurement
  • Strong command of power integrity and power delivery network design, including multi-rail architectures, power management IC selection, voltage sequencing, and board-level current limiting
  • Strong working experience with high-speed serial interface design, analysis and debug, particularly PCIe Gen 4/5 topology, configuration, and Ethernet

Nice to haves but not required:  

  • Experience writing basic firmware for hardware bring up and validation 
  • Hands-on embedded systems debug skills that let you move between careful pre-fab analysis and fast, practical problem-solving on the bench
  • Experience with COTS hardware for space applications, including radiation awareness, component derating, and upset mitigation techniques (ECC memory scrubbing, watchdog/reset architectures)
  • Hands-on experience with physical PCB layout, particularly for complex, high-layer-count boards with dense BGA packages
  • Familiarity with thermal management at the board and system level, including junction temperature modeling, thermal interface material selection, and collaborating with mechanical engineers on packaging solutions for high-TDP modules

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