Digital Design Engineer Intern Jobs in California

The High Speed Digital Design Engineer plays a key role in designing the core compute, communication, and monitoring platforms that power advanced vehicle charging and residential/industrial energy storage products. This role focuses on architecting and developing next-generation high-speed digital systems, including high-bandwidth data acquisition platforms, real-time control processors with multi-gigabit interfaces, and signal integrity-critical printed circuit boards. You will take designs from concept through production, ensuring robust performance, reliability, and manufacturability in demanding energy electronics applications.

• Architect and design high-speed digital systems and PCB assemblies for energy products, including platforms with DDR memory interfaces, Gigabit Ethernet, USB 3.x, PCIe, LVDS, and other multi-gigabit communication links.
• Own end-to-end hardware design from schematic capture and component selection through layout review, design optimization, bring-up, validation, and production release.
• Perform detailed signal integrity and power integrity analysis, including pre- and post-layout simulations, to establish and verify robust high-speed design margins.
• Configure and use SI/PI simulation tools to evaluate transmission line behavior, impedance matching, termination strategies, jitter, crosstalk, and return loss for high-speed interfaces.
• Guide and review PCB layout activities, including stack-up design, controlled impedance definition, floorplanning, layer assignment, via stitching, and plane partitioning for multi-Gbps signaling.
• Collaborate closely with mechanical, firmware, EMC, general low-voltage electrical, RF, design validation, thermal, compliance, reliability, and manufacturing test engineers to deliver integrated system solutions.
• Select and interface system-on-chips (SoCs), FPGAs, DDR memory devices, Ethernet PHYs, and high-speed transceivers appropriate for performance, cost, and reliability targets.
• Plan and execute bench validation and debug of high-speed digital circuits, including measuring eye diagram compliance against relevant communication protocols.
• Use high-speed lab equipment such as high-bandwidth oscilloscopes, TDR/TDT instruments, VNAs, BERTs, and protocol analyzers to characterize and troubleshoot designs.
• Develop and refine basic firmware configurations and bootloader settings related to high-speed interfaces, such as on-die terminations and device configuration registers.
• Create and use basic scripts to read, modify, and automate test procedures and data analysis for digital hardware validation.
• Document design decisions, analysis results, test plans, and validation outcomes to support design reviews and product certification.
• Support manufacturing test and production teams by providing guidance on test strategies, design-for-test considerations, and failure analysis for high-speed digital hardware.

• Bachelor’s degree in Electrical Engineering or equivalent experience with high-speed digital design.
• Hands-on experience designing high-speed digital circuits that incorporate DDR memory, PCIe, USB 3.x, Gigabit Ethernet, LVDS, or similar multi-gigabit interfaces.
• Strong understanding of signal integrity fundamentals, including transmission line theory, impedance matching, termination strategies, jitter, crosstalk, and return loss.
• Experience performing detailed signal integrity and power integrity simulations using tools such as HyperLynx, Ansys SIwave, Cadence Sigrity, ADS, HFSS, or equivalent.
• Proficiency in selecting and interfacing SoCs, FPGAs, DDR memory, Ethernet PHYs, and high-speed transceivers for complex digital systems.
• Experience in PCB stack-up design, controlled impedance routing, layer assignment, via stitching, and plane partitioning for multi-Gbps signaling.
• Demonstrated ability to perform or guide PCB layout, including stack-up definition, controlled impedance specification, and board-level floorplanning.
• Hands-on debug experience with high-speed lab equipment, including high-bandwidth oscilloscopes (greater than 4 GHz), TDR/TDT instruments, VNAs, BERTs, and protocol analyzers.
• Ability to perform bench validation and debug of high-speed interfaces, including measuring and interpreting eye diagrams for compliance with communication standards.
• Basic firmware skills sufficient to understand and adjust bootloader configurations and device settings, such as on-die terminations and interface configuration registers.
• Basic scripting ability to read, modify, and automate test procedures and data analysis for digital hardware validation.
• Strong collaboration skills and proven experience working effectively with cross-functional teams including LV electrical, RF, firmware, FPGA, layout, test, and manufacturing engineers.

• Experience with DDR memory and Ethernet interface design, including timing closure and layout optimization.
• Familiarity with additional digital interfaces such as SPI, I2C, and other serial communication protocols.
• Experience working with vendors to configure and validate IBIS models and other simulation data for signal integrity analysis.
• Exposure to EMC considerations and design practices for high-speed digital systems in complex electromechanical products.
• Background in energy, automotive, industrial, or other safety-critical electronic systems is beneficial.
• Strong documentation and communication skills for presenting analysis results, design trade-offs, and validation findings to technical stakeholders.

You will work in a collaborative engineering environment that brings together electrical, firmware, mechanical, RF, validation, thermal, compliance, reliability, and manufacturing test disciplines to create advanced energy and charging products. The role involves a mix of office-based design and analysis work using industry-standard SI/PI simulation and CAD tools, along with regular hands-on lab activities for hardware bring-up, validation, and debug using high-speed test equipment. You will engage in design reviews, cross-functional problem solving, and iterative prototyping to push the performance boundaries of energy electronics. The environment emphasizes technical excellence, rigorous testing, and close teamwork to deliver robust, scalable hardware platforms for real-world applications.

This is a Contract to Hire position based out of Palo Alto, CA.

The pay range for this position is $65.00 - $90.00/hr.

Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following: • Medical, dental & vision • Critical Illness, Accident, and Hospital • 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available • Life Insurance (Voluntary Life & AD&D for the employee and dependents) • Short and long-term disability • Health Spending Account (HSA) • Transportation benefits • Employee Assistance Program • Time Off/Leave (PTO, Vacation or Sick Leave)

This is a fully onsite position in Palo Alto,CA.

This position is anticipated to close on Aug 24, 2026.

About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.

The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.

If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email actalentaccommodation@actalentservices.com for other accommodation options.

San Francisco Fair Chance Ordinance: Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.

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Use of Artificial Intelligence (AI): We may use Artificial Intelligence (AI) to support parts of our hiring process, including sourcing, screening, and evaluating candidates. AI helps assess applications and qualifications, but final decisions are made by our hiring team. By applying, you acknowledge and agree that your application may be reviewed using AI tools.