1

Design For Test Dft Manager Jobs (NOW HIRING)

SOC DFT Intern - Summer 2027

Austin, TX ยท On-site

$14.75 - $19.75/hr

Digital Design - DFT Reports To: DFT Engineer / Manager About the Role: We are seeking a highly motivated and detail-oriented Design for Test (DFT) Intern to join our Digital Design team. As a DFT ...

Apply Design for Manufacturability (DFM) and Design for Test (DFT) best practices throughout ... Manage engineering change notices (ECNs), product revisions, and hardware lifecycle documentation.

Apply Design for Manufacturability (DFM) and Design for Test (DFT) best practices throughout ... Manage engineering change notices (ECNs), product revisions, and hardware lifecycle documentation.

DFT Engineer (MBIST) - Remote / C2C

Plano, TX ยท Remote

$139K - $143K/yr

Contract (Full-Time) We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using ...

Avionics Test Engineer

Saratoga, CA ยท On-site

$150K - $250K/yr

You will design test interface boards (TIBs), embed design-for-test (DFT) practices into the board design process, and plan and execute board-level testing for engineering model (EM) and ...

DFT Implementation Engineer

Austin, TX ยท On-site

$141K - $200K/yr

Your contributions will directly influence the quality and efficiency of Intel's products, ensuring seamless integration of Design for Test (DFT) capabilities in cutting-edge designs. This role ...

You will design test interface boards (TIBs), embed design-for-test (DFT) practices into the board design process, and plan and execute board-level testing for engineering model (EM) and ...

As a Design for Test Consultant, you will be part of a team contributing to implementing and verifying DFT features within our Enterprise Customer's (ASIC) products, as well as enabling them to ...

Physical Design Engineer

Sunnyvale, CA ยท On-site

$159K - $164K/yr

Chip-Level Floorplanning & Hierarchical Design - Manage top-level layout planning, pin assignments ... DFT Integration - Work with Design for Test (DFT) teams to ensure scan chain connectivity and ...

Support Design for Manufacturing (DFM) and Design for Test (DFT) to ensure smooth transition to mass production * Troubleshoot and resolve electrical issues during development, validation, and ...

Senior DFT Engineer

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

Showing results 41-60

Design For Test Dft Manager information

See salary details

$26.5K

$109.1K

$170.5K

How much do design for test dft manager jobs pay per year?

As of Sep 14, 2026, the average yearly pay for design for test dft manager in the United States is $109,109.00, according to ZipRecruiter salary data. Most workers in this role earn between $94,000.00 and $130,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Design For Test Dft Manager jobs?

For Design For Test Dft Manager jobs, the most frequently searched job titles are:

Infographic showing various Design For Test Dft Manager job openings in the United States as of August 2026, with employment types broken down into 88% Full Time, 11% Part Time, and 1% Contract. Highlights an 80% Physical, 2% Hybrid, and 18% Remote job distribution, with an average salary of $109,109 per year, or $52.5 per hour.

SOC DFT Intern - Summer 2027

Austin, TX โ€ข On-site

$14.75 - $19.75/hr

Full-time

Posted 7 days ago


Job description

Job Description
Job Title: DFT Intern
Location: Austin, TX (On-site/Hybrid)
Department: Digital Design - DFT
Reports To: DFT Engineer / Manager
About the Role:
We are seeking a highly motivated and detail-oriented Design for Test (DFT) Intern to join our Digital Design team. As a DFT Intern, you will work closely with experienced engineers to support the development and implementation of DFT methodologies for cutting-edge SoC designs. This internship offers hands-on experience in scan insertion, ATPG, MBIST, and other test-related flows in a real-world semiconductor environment.
Key Responsibilities:
  • Assist in the implementation of DFT techniques such as scan insertion, boundary scan, and memory BIST.
  • Support ATPG pattern generation and validation using industry-standard tools.
  • Help with test coverage analysis and debug of test patterns.
  • Collaborate with RTL designers and verification teams to ensure testability requirements are met.
  • Contribute to automation of DFT flows using scripting languages (e.g., Python, Perl, TCL).
  • Document DFT methodologies, test plans, and results.

Qualifications:
  • Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Strong understanding of digital logic design and VLSI fundamentals.
  • Familiarity with Verilog/VHDL and scripting languages (Python, Perl, or TCL).
  • Exposure to DFT concepts such as scan chains, ATPG, and BIST is a plus.
  • Experience with EDA tools from Synopsys, Cadence, or Mentor Graphics is desirable.
  • Excellent problem-solving skills and attention to detail.
  • Strong communication and teamwork abilities.

Preferred Skills (Nice to Have):
  • Coursework or project experience in DFT or digital IC design.
  • Knowledge of STA, synthesis, and RTL verification.
  • Familiarity with Linux/Unix environments.

What You'll Gain:
  • Hands-on experience with industry-standard DFT tools and flows.
  • Mentorship from experienced engineers in a collaborative environment.
  • Exposure to the full ASIC design and test cycle.
  • Opportunity to contribute to real silicon projects.

In order to be considered for a summer internship with NXP you must be returning to school or graduating at the conclusion of the internship term. If you are graduating prior to July 2027 please apply to Entry Level full-time roles.
More information about NXP in the United States...
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
#LI-e41b