DFT Engineer
Austin, TX ยท On-site
As a DFT Engineer you will work closely with all other design teams - backend, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT ...
Austin, TX ยท On-site
As a DFT Engineer you will work closely with all other design teams - backend, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT ...
Austin, TX ยท On-site
As a DFT Engineer you will work closely with all other design teams - backend, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT ...
Sunnyvale, CA ยท On-site
$146K - $209K/yr
As an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team, you will architect and implement testability solutions for complex, high-performance ASICs deployed at ...
Sunnyvale, CA ยท On-site
$146K - $209K/yr
As an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team, you will architect and implement testability solutions for complex, high-performance ASICs deployed at ...
Saratoga, CA ยท On-site
$120K - $220K/yr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
Saratoga, CA ยท On-site
$120K - $220K/yr
We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...
Austin, TX ยท On-site
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. * 8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows.
Austin, TX ยท On-site
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. * 8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows.
Austin, TX ยท On-site
$103K - $142K/yr
Key job responsibilities Define and develop state-of-the-art Design for Test (DFT) architectures ... technical guidance Manage project timelines and deliverables, ensuring high-quality DFT ...
Austin, TX ยท On-site
$103K - $142K/yr
Key job responsibilities Define and develop state-of-the-art Design for Test (DFT) architectures ... technical guidance Manage project timelines and deliverables, ensuring high-quality DFT ...
Westerville, OH ยท On-site
Define Design for Test (DFT) requirements early in product development. * Align engineering test ... Direct management of the Core Engineering Test Automation team * Influences product release ...
Westerville, OH ยท On-site
Define Design for Test (DFT) requirements early in product development. * Align engineering test ... Direct management of the Core Engineering Test Automation team * Influences product release ...
Santa Clara, CA ยท On-site
The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug. This is an excellent opportunity for a hands-on DFT Engineer ...
Santa Clara, CA ยท On-site
The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug. This is an excellent opportunity for a hands-on DFT Engineer ...
Austin, TX ยท On-site
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. * 8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows.
Austin, TX ยท On-site
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. * 8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows.
San Jose, CA ยท On-site
$194K/yr
Associate Experience Required: * 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement ...
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San Jose, CA ยท On-site
$194K/yr
Associate Experience Required: * 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement ...
The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test ... This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test ...
The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test ... This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test ...
Austin, TX ยท On-site
About the role Sambanova is looking for a talented and motivated Principal Design for Test (DFT) Engineer to help us build state-of-the-art RDU chips for machine learning and artificial intelligence.
Austin, TX ยท On-site
About the role Sambanova is looking for a talented and motivated Principal Design for Test (DFT) Engineer to help us build state-of-the-art RDU chips for machine learning and artificial intelligence.
San Jose, CA ยท On-site
... test hooks and observability * Built-in Self-Repair (BISR) for redundancy management * Drive fault ... Partner with physical design and packaging teams to optimize DFT area, timing, and package routing ...
San Jose, CA ยท On-site
... test hooks and observability * Built-in Self-Repair (BISR) for redundancy management * Drive fault ... Partner with physical design and packaging teams to optimize DFT area, timing, and package routing ...
Ability to read schematics, identify test point requirements, and perform Design for Test (DFT) analysis. * Experience with Quality Management tools and methodologies: PFMEA, PPAP, APQP, QRQC.
Ability to read schematics, identify test point requirements, and perform Design for Test (DFT) analysis. * Experience with Quality Management tools and methodologies: PFMEA, PPAP, APQP, QRQC.
San Jose, CA ยท On-site
$185K - $230K/yr
Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance. * Work closely with post-silicon teams to facilitate silicon bring-up and debug.
San Jose, CA ยท On-site
$185K - $230K/yr
Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance. * Work closely with post-silicon teams to facilitate silicon bring-up and debug.
Author standard operating procedures (SOPs), test coverage reports, and Design-for-Test (DFT) guidelines. Requirements: Qualifications & Skills * Education: Bachelor's in Electrical Engineering ...
Author standard operating procedures (SOPs), test coverage reports, and Design-for-Test (DFT) guidelines. Requirements: Qualifications & Skills * Education: Bachelor's in Electrical Engineering ...
Austin, TX ยท On-site
$99K - $135K/yr
Key job responsibilities โข Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes โข Work closely with block designers and physical design (PD) team ...
Austin, TX ยท On-site
$99K - $135K/yr
Key job responsibilities โข Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes โข Work closely with block designers and physical design (PD) team ...
Santa Clara, CA ยท On-site
$70 - $80/hr
Coordinate Design for Manufacturing (DFM), Design for Assembly (DFA), and Design for Test (DFT ... Strong experience managing New Product Introduction (NPI) programs for x86 hardware platforms.
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Santa Clara, CA ยท On-site
$70 - $80/hr
Coordinate Design for Manufacturing (DFM), Design for Assembly (DFA), and Design for Test (DFT ... Strong experience managing New Product Introduction (NPI) programs for x86 hardware platforms.
Plano, TX ยท Remote
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality. * Act as a technical escalation point for advanced DFT and post-silicon debug issues. * Mentor junior ...
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Plano, TX ยท Remote
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality. * Act as a technical escalation point for advanced DFT and post-silicon debug issues. * Mentor junior ...
San Jose, CA ยท On-site
... design-for-test (DFT) structures, and establish baseline yield limits. * Cross functional: Work ... Must be a self-driven engineer with good project management and organizational skills to deliver ...
San Jose, CA ยท On-site
... design-for-test (DFT) structures, and establish baseline yield limits. * Cross functional: Work ... Must be a self-driven engineer with good project management and organizational skills to deliver ...
OR ยท On-site +1
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
OR ยท On-site +1
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
$26.5K - $39.6K
3% of jobs
$39.6K - $52.7K
5% of jobs
$52.7K - $65.8K
5% of jobs
$65.8K - $78.9K
4% of jobs
$78.9K - $92K
4% of jobs
$93.6K is the 25th percentile. Wages below this are outliers.
$92K - $105K
21% of jobs
The median wage is $109.7K / yr.
$105K - $118.1K
18% of jobs
$127.8K is the 75th percentile. Wages above this are outliers.
$118.1K - $131.2K
18% of jobs
$131.2K - $144.3K
10% of jobs
$144.3K - $157.4K
6% of jobs
$157.4K - $170.5K
4% of jobs
$26.5K
$109.1K
$170.5K
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