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Design For Test Dft Manager Jobs (NOW HIRING)

DFT Engineer

Austin, TX ยท On-site

As a DFT Engineer you will work closely with all other design teams - backend, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT ...

ASIC Engineer, Design for Test

Sunnyvale, CA ยท On-site

$146K - $209K/yr

As an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team, you will architect and implement testability solutions for complex, high-performance ASICs deployed at ...

Senior DFT Engineer

Saratoga, CA ยท On-site

$120K - $220K/yr

We are seeking a Senior Design-for-Test (DFT) Engineer to join our SoC design team. In this role, you will be responsible for defining and implementing comprehensive DFT strategies across complex ...

Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. * 8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows.

The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug. This is an excellent opportunity for a hands-on DFT Engineer ...

Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. * 8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows.

About the role Sambanova is looking for a talented and motivated Principal Design for Test (DFT) Engineer to help us build state-of-the-art RDU chips for machine learning and artificial intelligence.

... test hooks and observability * Built-in Self-Repair (BISR) for redundancy management * Drive fault ... Partner with physical design and packaging teams to optimize DFT area, timing, and package routing ...

Coordinate Design for Manufacturing (DFM), Design for Assembly (DFA), and Design for Test (DFT ... Strong experience managing New Product Introduction (NPI) programs for x86 hardware platforms.

Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality. * Act as a technical escalation point for advanced DFT and post-silicon debug issues. * Mentor junior ...

... design-for-test (DFT) structures, and establish baseline yield limits. * Cross functional: Work ... Must be a self-driven engineer with good project management and organizational skills to deliver ...

Senior DFT Engineer

OR ยท On-site +1

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

Showing results 21-40

Design For Test Dft Manager information

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$26.5K

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How much do design for test dft manager jobs pay per year?

As of Sep 14, 2026, the average yearly pay for design for test dft manager in the United States is $109,109.00, according to ZipRecruiter salary data. Most workers in this role earn between $94,000.00 and $130,000.00 per year, depending on experience, location, and employer.

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Infographic showing various Design For Test Dft Manager job openings in the United States as of August 2026, with employment types broken down into 88% Full Time, 11% Part Time, and 1% Contract. Highlights an 80% Physical, 2% Hybrid, and 18% Remote job distribution, with an average salary of $109,109 per year, or $52.5 per hour.

DFT Engineer

Austin, TX โ€ข On-site

Full-time

Re-posted 27 days ago


Job description

Description
For an exciting well funded start-up we are looking for a DFT Engineer.
As a DFT Engineer you will work closely with all other design teams - backend, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT) methodologies for highly complex digital and mixed-signal chips. You will work on silicon test strategies, DFT/DFD, BIST for complex next generation SoCs.
Requirements
Minimum qualifications:
  • 5+ Experience in DFT specification definition, architecture, insertion, and analysis in designs
  • Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG-related issues
  • Experience in fault modeling

Preferred qualifications:
  • Master's degree in Electrical Engineering.
  • Experience in IP integration (memories, Test controllers, TAP, MBIST).
  • Experience using EDA Test tools like Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, and TestKompress.
  • Experience and understanding of ASIC DFT, synthesis, simulation and verification flow.
  • Excellent attention to detail organizational, problem-solving, and communication skills.

Responsibilities:
  • Implement SoC DFT strategy and architecture (ATPG/DFT/MBIST)
  • Work on hierarchical design
  • Debug all Design Rule checks, apply design fixes to achieve high test quality
  • Insert all DFT logic - boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
  • Insert and hook up MBIST logic.
  • Work on test plan for special analog IPs and implement.
  • Document DFT working processes.