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Ddr Validation Engineer Jobs (NOW HIRING)

Semiconductor Engineering

Candidates will be joining some of the brightest inventors and engineers in the world to develop ... The candidate is required to have experience with processor-memory interfaces, including DDR ...

Nutanix

#Pre-Silicon Validation Engineer

San Diego, CA · On-site

... Engineer to support the development and validation of complex ASIC and FPGA-based designs. The ... Knowledge of PCIe, CXL, DDR, Ethernet, or other high-speed interfaces.Experience with cloud-based ...

Qualcomm

#Pre-Silicon Validation Engineer

San Diego, CA · On-site

$98K - $147K/yr

Job Title Post-Silicon Validation Engineer Location San Diego, CA (Onsite) Job Summary We are ... Knowledge of PCIe, CXL, DDR, Ethernet, or other high-speed interfaces. * Experience with cloud ...

Apple

DRAM Design Validation Engineer

Cupertino, CA

$144K - $218K/yr

As our DRAM Design Validation Engineer, you will be ensuring the successful integration of DRAM ... IO (DDR/DDR2/DDR3/DDR4/DDR5) characterization and qualification Understanding of memory test ...

Apple

DRAM Design Validation Engineer

Cupertino, CA

$175K - $311K/yr

As our DRAM Design Validation Engineer, you will be ensuring the successful integration of DRAM ... IO (DDR/DDR2/DDR3/DDR4/DDR5) characterization and qualification Understanding of memory test ...

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How much do ddr validation engineer jobs pay per hour?

As of Sep 11, 2026, the average hourly pay for ddr validation engineer in the United States is $52.00, according to ZipRecruiter salary data. Most workers in this role earn between $39.42 and $63.22 per hour, depending on experience, location, and employer.

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Infographic showing various Ddr Validation Engineer job openings in the United States as of August 2026, with employment types broken down into 94% Full Time, 2% Part Time, and 4% Contract. Highlights an 85% Physical, 5% Hybrid, and 10% Remote job distribution, with an average salary of $108,152 per year, or $52 per hour.

Principal Debug Validation Engineer

Austin, TX • On-site

Graphcore
See more jobs at Graphcoreexternal

Full-time

Re-posted 17 days ago

Job description

Principal Embedded SW/FW Engineer (Bringup) - Austin, Tx, USA

Job Summary

We have an exciting opportunity to be part of a collaborative, cross-functional development team validating cutting-edge, high-performance AI chips and platforms.

 You will play a key role in supporting new product introductions and post-silicon validation.

Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to provide technical guidance to other engineering team members. In this role, you can leverage our experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes.

The Team

The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team.

Responsibilities and Duties

  • Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon
  • Deploy silicon validation tests on first silicon and debugging them
  • Develop automated test framework and regression test suites in Python to optimize validation efficiency
  • Collaborate closely with engineers from many other disciplines on a variety of topics
  • Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies
  • Analyse test results, identify and debug failures/defects
  • Contribute to shared test and validation infrastructure
  • Provide feedback to architects

Candidate Profile 

Essential:

  • Understanding of ML applications and their workloads
  • A self-starter who can apply independent judgement
  • A team player able to lead and support colleagues with difficult concepts
  • Strong experience in Bare metal / embedded C/C++
  • Excellent problem-solving, analytical & diagnostic skills
  • Ability to work across teams and programming languages to find root causes of critical and complex issues
  • Experience of the post-silicon validation process applied in digital ASIC environments
  • Python, Linux
  • Excellent communication skills and the ability to explain difficult concepts to resolve issues 

Desirable

  • 5 to 10 years' experience 
  • Experience building and leading, multi-site teams
  • Driver level experience with one or more of the following is highly desirable:
    • PCIe
    • Ethernet
    • Memory technologies (LPDDR, DDR, HBM, ...)
    • Other peripherals such as I2C, I3C, SPI, ...
  • Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable.
  • Experience of Arm CPUs, System IP and debug tools.
  • Experience of AMBA protocols.
  • Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, 

Apply