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Ddr Validation Engineer Jobs (NOW HIRING)

Apple

Silicon Validation Engineer

San Francisco, CA · On-site

As a DDR Silicon Validation Engineer, you will be at the forefront of innovation, performing critical lab characterization and validation of advanced analog and mixed-signal embedded circuits. This ...

Apple

Silicon Validation Engineer

Bodega Bay, CA · On-site

$184K - $324K/yr

As a DDR Silicon Validation Engineer, you will be at the forefront of innovation, performing critical lab characterization and validation of advanced analog and mixed-signal embedded circuits. This ...

Apple

Silicon Validation Engineer

Bodega Bay, CA · On-site

$129K - $225K/yr

As a DDR Silicon Validation Engineer, you will be at the forefront of innovation, performing critical lab characterization and validation of advanced analog and mixed-signal embedded circuits. This ...

Apple

DRAM Design Validation Engineer

Cupertino, CA · On-site

As our DRAM Design Validation Engineer, you will be ensuring the successful integration of DRAM ... understanding DDR-PHY and Memory Controller Experience in LPDDR IO (DDR/DDR2/DDR3/DDR4/DDR5 ...

Apple

DRAM Design Validation Engineer

Cupertino, CA · On-site

As our DRAM Design Validation Engineer, you will be ensuring the successful integration of DRAM ... understanding DDR-PHY and Memory Controller Experience in LPDDR IO (DDR/DDR2/DDR3/DDR4/DDR5 ...

Lattice

Silicon Validation Engineer 5

San Jose, CA · On-site

FPGA consists of various IPs as a building block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, Fabric, I/O etc.As a Silicon Design Validation engineer, you will have an ...

Cypress HCM

Senior System Validation Engineer

San Jose, CA · Hybrid

$122K - $167K/yr

Collaborate on DDR system validation, including DDR topologies, protocols, and compliance. * Work ... S. or M.S. in Computer Engineering, Electrical Engineering, or related field. * 5+ years of ...

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How much do ddr validation engineer jobs pay per hour?

As of Sep 11, 2026, the average hourly pay for ddr validation engineer in the United States is $52.00, according to ZipRecruiter salary data. Most workers in this role earn between $39.42 and $63.22 per hour, depending on experience, location, and employer.

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Infographic showing various Ddr Validation Engineer job openings in the United States as of August 2026, with employment types broken down into 94% Full Time, 2% Part Time, and 4% Contract. Highlights an 85% Physical, 5% Hybrid, and 10% Remote job distribution, with an average salary of $108,152 per year, or $52 per hour.

Senior Memory Validation Engineer - DDR/HBM, Silicon Bring-up | Mountain View, CA (On-site)

Mountain View, CA • On-site

Brickred Systems
IT Services • 51 - 200 employees
Learn more about Brickred Systemsexternal

Other

Re-posted 3 days ago

Job description

Senior Memory Validation Engineer DDR/HBM, Silicon Bring-up

BrickRed Systems Mountain View, California, United States (On-site)

We are seeking a highly experienced Senior Memory Validation Engineer to join our Silicon Semiconductor AI Project team. In this hands-on role, you will focus on DDR and HBM bring-up and validation, covering physical, electrical, and software aspects of silicon development. This position offers an opportunity to work directly in lab settings with cutting-edge silicon chips.

Apply now to be a part of this high-impact, hands-on engineering team!

What You'll Do

  • Perform DDR and HBM subsystem bring-up, validation, and characterization
  • Handle test generation, pattern development, and test infrastructure setup
  • Conduct electrical measurements and execute silicon debug processes
  • Work extensively with logic analyzers, oscilloscopes, and other lab equipment
  • Collaborate with cross-functional teams and contribute to lab-based experimentation (80% hands-on)

Key Qualifications

  • Bachelor's degree in Engineering (required)
  • 10+ years of experience in memory validation and silicon bring-up
  • Hands-on lab experience and proven DDR validation expertise (mandatory)

Experience with:

  • Memory Electrical Characterization Jitter measurement, Shmoo testing
  • C/C++ and Python programming
  • Memory patterns and stress generators
  • Silicon debug for logic, software, and physical issues
  • System architecture, performance/power optimization

Top Skills We're Looking For

  • Minimum 10 years' experience in memory validation and characterization (e.g., Shmoo, offset testing)
  • Minimum 10 years' experience using C/Python for validation tasks
  • Minimum 10 years' experience working collaboratively in lab environments

Soft Skills

  • Strong problem-solving and communication skills
  • Highly self-motivated, organized, and team-oriented
  • Ability to triage complex technical issues quickly and accurately

Why Join Us?

This role places you at the center of hands-on silicon chip validation for one of the industry's leading semiconductor projects. If you're passionate about performance, power, and pushing memory technology forward, this is your opportunity.