Cpu Rtl Design Engineer Jobs in Porter Ranch, CA

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.
The mission of Amazon Leo Government (ALG) team is to leverage existing Kuiper technology and provide high speed, low latency, and secure satellite broadband services to the United States and our allied government customers.
The Senior DSP Engineer will play a pivotal role in the team delivering innovative and fast-paced analysis and design solutions, focusing on satellite and ground system design and analysis as well as on the design of the various phased array communication system needs (link budget, beamforming, calibration, compensation, etc.) of the electronics sub-systems. They will be expected to lead a variety of tasks, from DSP design and algorithm selection, to FPGA implementation and board bring-up and test. They will work across teams and support fellow engineers with design reviews and the preparation of joint reports and proposals

The candidate will have a sharp focus on the specific needs of the customer and be able to conduct trades and analyses to show that proposed solutions will meet the customer's goals.
The successful candidate will have demonstrated experience working on complex programs with a diverse set of talented individuals, as well as with partner organizations (including government agencies). The candidate will exhibit the potential to lead small sub-teams of electrical engineers, and be able to prepare easy-to-read and technically compelling written reports.
CODE-10037
Key job responsibilities
- Interact directly with customers to understand technical requirements, and translate them into technically robust solutions backed by data and analysis.
- Design and develop DSP algorithms for phased array antenna communication systems including beamforming, beam steering, null steering, and adaptive array processing.
- Develop and validate signal processing chains in MATLAB and Simulink, including fixed-point modeling and bit-true simulations.
- Implement and optimize FFT/iFFT architectures for OFDM waveforms, channelization, spectral analysis, and frequency-domain beamforming.
- Collaborate with RF engineers, antenna engineers, and systems engineers to define interface requirements and performance budgets.
- Analyze system performance metrics (EVM, BER, SINR, beam patterns, sidelobe levels) and optimize DSP implementations.
- Develop calibration algorithms for phased array systems including amplitude/phase correction, mutual coupling compensation, and array manifold characterization.
- Model and simulate RF impairments (I/Q imbalance, phase noise, nonlinearity) and develop DSP-based mitigation techniques.
- Perform trade studies on algorithm complexity, latency, throughput, and resource utilization
- Deliver well-written documentation, reports, and presentations for technical design reviews and as part of proposal efforts.
- Design and support test campaigns, both development and qualification/acceptance, for space hardware.
Security Clearance: This position requires that the candidate selected be a US Citizen and candidates must be able to obtain and maintain a US Government security clearance of TS/SCI.
A day in the life
Basic qualifications
Bachelor's Degree in Electrical or Computer Engineering or related discipline, or equivalent experience
7+ years of experience in hardware development across the full product life cycle (concept to production)
7+ years of electrical engineering work experience in Space, Aerospace/Defense, Automotive, and/or Communications fields or combination thereof.
7+ years of experience with DSP algorithm development and hardware test system debugging.
Preferred qualifications
- Master's or PhD degree in Electrical or Computer Engineering or related discipline.
- Translate DSP algorithms from MATLAB/Simulink models to synthesizable HDL (VHDL/Verilog) using HDL Coder or manual RTL design.
- Architect efficient FPGA implementations of DSP processing chains with pipelining, parallelism, and resource sharing strategies
- Implement digital down-converters (DDC), digital up-converters (DUC), polyphase filter banks, and channelizers in Matlab / Simulink / RTL.
- Perform FPGA synthesis, timing closure, and resource optimization for Xilinx UltraScale+/Versal or Intel Agilex devices
- Verify RTL designs against MATLAB/Simulink golden reference models using co-simulation.
- Track record of successfully delivering compelling written reports and complete designs on time, to scope, with high quality.
- High sense of ownership, urgency, and drive; resourceful, and able to deliver results with minimal direction.
- Excellent oral and written communication skills.
- Demonstrated experience working with government agencies.
- US Security Clearance