Wireless SoC Design Engineer
$120.30K - $210.10K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
Wireless SoC Design Engineer
$120.30K - $210.10K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
Wireless SoC Design Engineer
$171.60K - $302.20K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
Wireless SoC Design Engineer
$171.60K - $302.20K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
Senior ASIC Design Engineer - Terawave
Los Angeles, CA · On-site
$197.53K - $276.54K/yr
Review RTL, test plans, and implementation results to maintain high design quality. * Identify and mitigate technical risks early in the development cycle. * Mentor junior engineers and help ...
Senior ASIC Design Engineer - Terawave
Los Angeles, CA · On-site
$197.53K - $276.54K/yr
Review RTL, test plans, and implementation results to maintain high design quality. * Identify and mitigate technical risks early in the development cycle. * Mentor junior engineers and help ...
Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · On-site
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · On-site
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · On-site
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · On-site
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Wireless SoC Design Engineer
$171.60K - $302.20K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
Wireless SoC Design Engineer
$171.60K - $302.20K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Description In this role you will work on a small team designing CPU-based subsystems for high ...
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Principal ASIC Physical Design Engineer
$190K - $280K/yr
Engineered to survive the harshest radiation environments and to fully capitalize on today's and ... You will own the full physical design flow--from RTL handoff to GDSII--and collaborate closely with ...
Quick apply
Principal ASIC Physical Design Engineer
$190K - $280K/yr
Engineered to survive the harshest radiation environments and to fully capitalize on today's and ... You will own the full physical design flow--from RTL handoff to GDSII--and collaborate closely with ...
Senior ASIC Design Verification Engineer
$170K - $250K/yr
Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test. * Support silicon bring-up and post-silicon ...
Quick apply
Senior ASIC Design Verification Engineer
$170K - $250K/yr
Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test. * Support silicon bring-up and post-silicon ...
ASIC Design Verification Engineer
$130K - $200K/yr
You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...
Quick apply
ASIC Design Verification Engineer
$130K - $200K/yr
You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...
Physical Design Engineer in California
$138K - $142K/yr
Hi, Physical Design Engineer Santa Clara, CA - 5 days onsite no remote Longterm Full-Time / ... The ideal candidate will have strong hands-on expertise in RTL-to-GDSII implementation and signoff ...
Physical Design Engineer in California
$138K - $142K/yr
Hi, Physical Design Engineer Santa Clara, CA - 5 days onsite no remote Longterm Full-Time / ... The ideal candidate will have strong hands-on expertise in RTL-to-GDSII implementation and signoff ...
Senior FPGA Engineer, LEO Payload FPGA
$139.30K - $179K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, LEO Payload FPGA
$139.30K - $179K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, LEO Payload FPGA
$139.30K - $179K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, LEO Payload FPGA
$139.30K - $179K/yr
... design engineer will work with systems teams to define/develop/implement/test/release FPGA based ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, LEO Payload FPGA
Northridge, CA · On-site
$139.30K - $179K/yr
The FPGA design engineer will work with systems teams to define/develop/implement/test/release FPGA ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
Senior FPGA Engineer, LEO Payload FPGA
Northridge, CA · On-site
$139.30K - $179K/yr
The FPGA design engineer will work with systems teams to define/develop/implement/test/release FPGA ... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ...
FPGA Design Engineer
Los Angeles, CA · On-site
$100K - $140K/yr
FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware ...
FPGA Design Engineer
Los Angeles, CA · On-site
$100K - $140K/yr
FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a silicon design group with a ...
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a silicon design group with a ...
Wireless SOC FW Engineer
Los Angeles, CA · On-site
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a silicon design group with a ...
Wireless SOC FW Engineer
Los Angeles, CA · On-site
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a silicon design group with a ...
Wireless SOC FW Engineer
Los Angeles, CA · On-site
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a silicon design group with a ...
Wireless SOC FW Engineer
Los Angeles, CA · On-site
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a silicon design group with a ...
Cpu Rtl Design Engineer information
See Porter Ranch, CA salary details
$41.6K - $52.6K
2% of jobs
$52.6K - $63.6K
11% of jobs
$69.5K is the 25th percentile. Wages below this are outliers.
$63.6K - $74.6K
23% of jobs
The median wage is $81.7K / yr.
$74.6K - $85.6K
22% of jobs
$85.6K - $96.6K
17% of jobs
$96.9K is the 75th percentile. Wages above this are outliers.
$96.6K - $107.6K
9% of jobs
$107.6K - $118.6K
6% of jobs
$118.6K - $129.7K
3% of jobs
$129.7K - $140.7K
3% of jobs
$140.7K - $151.7K
2% of jobs
$151.7K - $162.7K
1% of jobs
$41.6K
$90.5K
$162.7K
How much do cpu rtl design engineer jobs pay per year?
As of May 31, 2026, the average yearly pay for cpu rtl design engineer in Porter Ranch, CA is $90,476.00, according to ZipRecruiter salary data. Most workers in this role earn between $69,800.00 and $101,100.00 per year, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?
To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.
What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?
CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.
What are CPU RTL Design Engineers?
CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?
| Aspect | Cpu Rtl Design Engineer | Cpu Verification Engineer |
|---|---|---|
| Primary Focus | Designing and developing RTL code for CPU components | Verifying and testing RTL designs for correctness |
| Skills & Certifications | HDL languages (Verilog/VHDL), FPGA/ASIC design experience | HDL, testbench development, simulation tools |
| Work Environment | Design teams, hardware development labs | Verification teams, simulation environments |
| Industry Usage | Semiconductor companies, CPU design firms | ASIC/FPGA verification, chip validation |
While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.
What are popular job titles related to Cpu Rtl Design Engineer jobs in Porter Ranch, CA? For Cpu Rtl Design Engineer jobs in Porter Ranch, CA, the most frequently searched job titles are:
What job categories do people searching Cpu Rtl Design Engineer jobs in Porter Ranch, CA look for? The top searched job categories for Cpu Rtl Design Engineer jobs in Porter Ranch, CA are:
What cities near Porter Ranch, CA are hiring for Cpu Rtl Design Engineer jobs? Cities near Porter Ranch, CA with the most Cpu Rtl Design Engineer job openings:
$120.30K - $210.10K/yr
Full-time
Medical, Dental, Retirement
Posted 16 days ago
Apple rating
8.1
Based on 661 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Come and join Apple’s growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply.
Description
In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. As a member of the team, you will work closely with SoC architects and IP developers to develop SoCs that meet the power, performance, and area goals for Apple devices, with a particular focus on low power metrics. You will engage in hardware/software/power partitioning discussions alongside software, firmware, and platform engineering teams. You will integrate industry standard and custom hardware IPs into SoCs. This is a highly visible role, where you will be at the center of the ASIC design efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers.","responsibilities":"Writing micro-architecture and design specifications.
Coding design in SystemVerilog following established design guidelines, owning all aspects of RTL development design.
Integrate IP blocks and optimize memories/hard macros required for the block.
Supporting verification efforts at multiple levels.
Checking your design with industry standard static tools such as LINT, CDC, RDC.
Analyzing and optimizing area, timing, and power.
Collaborate with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.
Preferred Qualifications
Familiarity with the ASIC design flow.
Knowledge of digital design, SoC architecture, and HDL languages like Verilog.
Shown experience writing micro-architecture specifications and converting them to design
Exposure to design methodologies and industry standard EDA tools.
Experience with AXI/AHB bus fabric and processor sub-systems.
Understanding of UPF and low-power design & implementation techniques.
Self-starter and willingness to learn.
Minimum Qualifications
Minimum requirements of bachelor's degree.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $120,300 and $210,100, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Description
In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. As a member of the team, you will work closely with SoC architects and IP developers to develop SoCs that meet the power, performance, and area goals for Apple devices, with a particular focus on low power metrics. You will engage in hardware/software/power partitioning discussions alongside software, firmware, and platform engineering teams. You will integrate industry standard and custom hardware IPs into SoCs. This is a highly visible role, where you will be at the center of the ASIC design efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers.","responsibilities":"Writing micro-architecture and design specifications.
Coding design in SystemVerilog following established design guidelines, owning all aspects of RTL development design.
Integrate IP blocks and optimize memories/hard macros required for the block.
Supporting verification efforts at multiple levels.
Checking your design with industry standard static tools such as LINT, CDC, RDC.
Analyzing and optimizing area, timing, and power.
Collaborate with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.
Preferred Qualifications
Familiarity with the ASIC design flow.
Knowledge of digital design, SoC architecture, and HDL languages like Verilog.
Shown experience writing micro-architecture specifications and converting them to design
Exposure to design methodologies and industry standard EDA tools.
Experience with AXI/AHB bus fabric and processor sub-systems.
Understanding of UPF and low-power design & implementation techniques.
Self-starter and willingness to learn.
Minimum Qualifications
Minimum requirements of bachelor's degree.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $120,300 and $210,100, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976