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Cpu Rtl Design Engineer Jobs in Phoenix, AZ (NOW HIRING)

Viasat, Inc.

FPGA Engineer (Space)

Tempe, AZ · On-site

$164K - $246K/yr

Own the architecture, design, and implementation of FPGA based digital systems * Develop RTL in ... Bachelor Degree in Electrical Engineering, Computer Engineering or a related field * 6+ years FPGA ...

Viasat, Inc.

FPGA Engineer (Space)

Tempe, AZ · On-site

$164K - $246K/yr

Own the architecture, design, and implementation of FPGA based digital systems * Develop RTL in ... Bachelor Degree in Electrical Engineering, Computer Engineering or a related field * 6+ years FPGA ...

Viasat, Inc.

FPGA Engineer (Space)

Tempe, AZ

$164K - $246K/yr

Own the architecture, design, and implementation of FPGA based digital systems * Develop RTL in ... Bachelor Degree in Electrical Engineering, Computer Engineering or a related field * 6+ years FPGA ...

Intel

Physical Design Methodology Engineer

Phoenix, AZ · On-site

$164K - $269K/yr

As a process technology design engineer, you will be responsible for creating methodologies, models ... Able to independently complete Netlist RTL-GDS place and route (APR), signoff tasks. Preferred ...

Viasat, Inc.

FPGA Engineer (Space)

Tempe, AZ · On-site

$129K - $194K/yr

What you'll do As a FPGA Engineer on the Space Infrastructure team, you will design, implement, and ... Contribute to architecture, design, and implementation of FPGA based digital systems * Develop RTL ...

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All JobsCpu Rtl Design Engineer JobsCpu Rtl Design Engineer Jobs in Phoenix, AZ

Cpu Rtl Design Engineer information

See Phoenix, AZ salary details

$38.4K

$83.6K

$150.3K

How much do cpu rtl design engineer jobs pay per year?

As of Jul 13, 2026, the average yearly pay for cpu rtl design engineer in Phoenix, AZ is $83,615.00, according to ZipRecruiter salary data. Most workers in this role earn between $64,500.00 and $93,400.00 per year, depending on experience, location, and employer.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are CPU RTL Design Engineers?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
What are popular job titles related to Cpu Rtl Design Engineer jobs in Phoenix, AZ? For Cpu Rtl Design Engineer jobs in Phoenix, AZ, the most frequently searched job titles are:
What job categories do people searching Cpu Rtl Design Engineer jobs in Phoenix, AZ look for? The top searched job categories for Cpu Rtl Design Engineer jobs in Phoenix, AZ are:
Cpu Rtl Design Engineer jobs near you
Senior FPGA Design Engineer

Senior FPGA Design Engineer

COMTECH TELECOMMUNICATIONS

Chandler, AZ • On-site

$101K - $136K/yr

Full-time

Re-posted 14 days ago

Job description


Job Title: Senior FPGA Engineer III

Department: Engineering->Platforms->FPGA SoC Group

Reports To: Director, Platforms

FLSA Status: Exempt

Last Modified: 9/10/2025

Level: T3

Location Chandler, AZ – Onsite 5 Days a week

Company Overview

Comtech Telecommunications Corp. is a leading global technology company providing terrestrial and wireless network solutions, next-generation 9-1-1 emergency services, satellite and space communications technologies, and cloud-native capabilities to commercial and government customers around the world. Our unique culture of innovation and employee empowerment unleashes a relentless passion for customer success. With multiple facilities located in technology corridors throughout the United States and around the world, Comtech leverages our global presence, technology leadership, and decades of experience to create the world’s most innovative communications solutions. For more information, please visit www.comtech.com.
We’re seeking curious, growth-minded thinkers to help shape our vision, structures, and systems; playing a key role as we launch into our ambitious future. If you’re invigorated by our mission, values, and drive to change the world — we’d love to have you apply.


Position Summary

Senior FPGA Designer with experience in the entire design flow for complex FPGA’s.

Responsibilities

  • Design, develop, document, debug and test FPGA SoC systems; including:
    1. IP Integration into FPGA Projects (synthesis/implementation)
    2. High-Performance FPGA IP (VHDL/SystemVerilog)
    3. Userspace Drivers for FPGA IP (C++)
    4. Firmware for Embedded Microcontrollers (C)
  • Utilize strong communication skills to effectively work and communicate with team members and engineering management.

Qualifications

  • Strong digital design engineer with FPGA/ASIC SoC design experience
  • Strong FPGA Implementation with Altera Quartus or Xilinx Vivado
  • Experience designing/debugging SoC systems with AMBA-compliant AXI and APB interfaces
  • Experience designing fmax-optimized, high-throughput, pipelined AXI-Stream IP
  • Capable of creating RTL simulations to identify and resolve most issues before hardware tests
  • Knowledgeable in Static Timing Analysis (STA) and Synopsis Design Constraints (SDC)
  • Experience analyzing STA reports and post-synth netlist/placement to resolve failing paths
  • Experience contributing to schematic capture and layout for FPGA portions of PCB designs
  • Experience implementing at least one Gigabit Transceiver Protocol:
    1. PCI Express, Interlaken, USB SuperSpeed
    2. 1000BASE-X/SGMII, 10GBASE-R, 40GBASE-4, 100GBASE-R4
  • Experience implementing Network Protocols, such as:
    • L1: IEEE 802.3, Cisco, Q/SFP+ MSA standards for Ethernet (1G to 100G)
    • L2/L3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCP
    • L4: VITA 49.2, IEEE-ISTO 4900 Digital IF Interoperability Standard (DIFI) and/or eCPRi
      (Highly Desired)
  • Proficient in SW development with C, C++ and GIT version control
  • Proficient in Microsoft Office Tools (Word, Excel, PowerPoint, Visio, etc.)
  • Demonstrated experience supporting multi-disciplinary, cross functional and matrixed teams

Desired Qualifications

  • Working knowledge of digital IF streams such as VITA 49.2, DIFI and/or eCPRi (Highly Desired)
  • Working knowledge of Embedded Linux: Kernel / Yocto / U-Boot / DeviceTree
  • Working knowledge with SATCOM waveforms like DVB-S2X and/or 5G NTN 3GPP Rel 17/18
  • Working knowledge of communication networks and security within a zero-trust environment
  • Experience with Partial Reconfiguration/DFX or PCIe CvP
  • Possess an active DoD clearance or demonstrate readiness to obtain one

Education

  • Bachelors in Electrical or Computer Engineering (or related degree).

Experience:

  • 5+ years of FPGA/ASIC SoC design experience.


Comtech Telecommunications Corp. is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability protected veteran status or other characteristics protected by law.