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Cpu Rtl Design Engineer Jobs in Phoenix, AZ (NOW HIRING)

Microchip Technology

Principal Engineer-Design

Chandler, AZ · On-site

  • Medical

  • Retirement

... engineering team and lead development of digital IP and SoC-level integration for mixed-signal ... This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ...

Microchip Technology

Principal Engineer-Design

Chandler, AZ · On-site

  • Medical

  • Retirement

... engineering team and lead development of digital IP and SoC-level integration for mixed-signal ... This is a hands-on role spanning RTL design, integration, and signoff verification-with broad cross ...

Intel

Senior CPU Performance Architect

Phoenix, AZ · On-site

$165K/yr

  • Medical

  • Retirement

  • PTO

Collaborates with architects, design, verification, and validation engineers during the execution ... Participates in the debug and fixing of performance miscorrelation between RTL and\or silicon ...

Viasat, Inc.

Hardware Design Engineer

Tempe, AZ · On-site

$164K - $246K/yr

Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Design high-speed interfaces (DDR4, SERDES, UART, I2C, SPI, LVDS) and perform signal/power ...

Viasat

Hardware Design Engineer

Tempe, AZ · On-site

$133 - $247/hr

Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Design high-speed interfaces (DDR4, SERDES, UART, I2C, SPI, LVDS) and perform signal/power ...

New

Viasat, Inc.

Hardware Design Engineer

Tempe, AZ

$164K - $246K/yr

Develop, simulate, and verify FPGA RTL (using SystemVerilog, Verilog, or VHDL) for control, data ... Design high-speed interfaces (DDR4, SERDES, UART, I2C, SPI, LVDS) and perform signal/power ...

New

Intel

Sr. Logic Design Engineer

Phoenix, AZ

$141K - $200K/yr

  • Medical

  • Retirement

  • PTO

Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly ... RTL/Logic design using System Verilog Language * Experience with Design of Data path, Power ...

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Cpu Rtl Design Engineer information

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$36.9K

$80.3K

$144.4K

How much do cpu rtl design engineer jobs pay per year?

As of Aug 18, 2026, the average yearly pay for cpu rtl design engineer in Phoenix, AZ is $80,330.00, according to ZipRecruiter salary data. Most workers in this role earn between $62,000.00 and $89,800.00 per year, depending on experience, location, and employer.

What is a CPU RTL design engineer?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.

What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are popular job titles related to Cpu Rtl Design Engineer jobs in Phoenix, AZ?

For Cpu Rtl Design Engineer jobs in Phoenix, AZ, the most frequently searched job titles are:

What job categories do people searching Cpu Rtl Design Engineer jobs in Phoenix, AZ look for?

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Cpu Rtl Design Engineer jobs near you
Infographic showing various Cpu Rtl Design Engineer job openings in Phoenix, AZ as of August 2026, with employment types broken down into 87% Full Time, 8% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $87,525 per year, or $42.1 per hour.

Staff Engineer, Digital Design Engineering (AI/ML)

Analog Devices

Chandler, AZ • On-site

Full-time

Re-posted 2 days ago

Analog Devices rating

8.5

Company rating: 8.5 out of 10

Based on 17 frontline employees who took The Breakroom Quiz

33rd of 159 rated electronics manufacturers

Job description

About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed-signal and power management ICs. You will apply AI/ML techniques to improve design automation, optimization, and productivity across the digital design flow. Your work will contribute to products spanning multiple business units, directly supporting how ADI integrates advanced digital functionality into next-generation products.
Key Responsibilities
  • Apply AI/ML methodologies to improve synthesis results, timing closure, power estimation, and design space exploration
  • Develop and implement digital subsystems for mixed-signal ICs, including control logic, digital interfaces, and on-chip processing blocks
  • Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power targets
  • Perform synthesis with timing and placement constraints (Genus), static timing analysis and power analysis (Tempus), and logical equivalence checking (Conformal)
  • Participate in architecture and design reviews, contributing technical analysis on timing, area, power, and testability trade-offs
  • Collaborate with analog design teams to implement and integrate digital-analog interfaces and control architectures
Required Skills and Experience
  • MSEE or MSCE with 7+ years of digital IC design experience, or PhD with 5+ years (BSEE/BSCE with equivalent depth considered)
  • Strong RTL design skills in Verilog/SystemVerilog with experience delivering complex digital subsystems
  • Demonstrated ability to deliver digital designs through tape-out, silicon validation, and production release
  • Solid scripting skills (Python, Tcl, shell) with experience applying AI/ML techniques to enhance productivity
  • Knowledge of synthesis, static timing analysis, DFT (scan, ATPG, BIST), and clock domain crossing methodologies
  • Proficiency with Cadence digital design tools: Genus, Innovus, Tempus, Conformal
  • Excellent presentation, technical writing, and communication skills
Preferred Qualifications
  • Curiosity and initiative to explore AI/ML techniques and emerging tools that can transform design workflows, with an enthusiasm for discovering more effective ways of working
  • Working knowledge of place-and-route (Innovus), floorplanning, and physical-aware design techniques
  • Experience with low-power design techniques including multi-voltage domains, power gating, and UPF
  • Familiarity with digital interfaces (I2C, SPI, UART) and mixed-signal SoC integration
  • Strong analytical and problem-solving abilities
Technical Scope
  • Application of AI/ML-driven workflows to improve design quality, turnaround time, or coverage
  • Block-level digital subsystem ownership from specification through silicon bring-up and production validation
  • Clock domain crossing analysis, lint, and formal verification for multi-clock digital architectures
  • DFT implementation including scan insertion, ATPG pattern generation, and fault coverage closure
Collaboration and Impact
  • Share AI/ML-driven improvements to digital design workflows and best practices with team members
  • Work with analog design, verification, and applications teams to implement digital control architectures that meet system-level requirements
  • Contribute to design reviews and cross-team technical discussions

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days

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About Analog Devices

Sourced by ZipRecruiter

Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect.

Industry

Electrical equipment, appliance, and component manufacturing

Company size

5,001 - 10,000 Employees

Headquarters location

Norwood, MA, US

Year founded

1965

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