Engineer II-Design
Allentown, PA · On-site
General RTL and ASIC development * Detailed module design, performance analysis and detailed design ... Bachelor's in Electrical Engineering, Computer Engineering or Computer Science. * Design courses ...
Allentown, PA · On-site
General RTL and ASIC development * Detailed module design, performance analysis and detailed design ... Bachelor's in Electrical Engineering, Computer Engineering or Computer Science. * Design courses ...
Allentown, PA · On-site
General RTL and ASIC development * Detailed module design, performance analysis and detailed design ... Bachelor's in Electrical Engineering, Computer Engineering or Computer Science. * Design courses ...
General RTL and ASIC development * Detailed module design, performance analysis and detailed design ... Bachelor's in Electrical Engineering, Computer Engineering or Computer Science. * Design courses ...
General RTL and ASIC development * Detailed module design, performance analysis and detailed design ... Bachelor's in Electrical Engineering, Computer Engineering or Computer Science. * Design courses ...
King Of Prussia, PA · On-site
$124K - $220K/yr
... RTL design and development utilizing VHDL, Verilog, and/or SystemVerilog • Support hardware ... engineering, and verification teams • Support full FPGA/ASIC lifecycle execution including ...
King Of Prussia, PA · On-site
$124K - $220K/yr
... RTL design and development utilizing VHDL, Verilog, and/or SystemVerilog • Support hardware ... engineering, and verification teams • Support full FPGA/ASIC lifecycle execution including ...
Exton, PA · On-site
$125K - $161K/yr
Design, implement, and verify FPGA logic primarily targeting Xilinx FPGAs using Vivado * Develop RTL using Verilog and/or VHDL * Perform FPGA verification, including simulation, synthesis, timing ...
Quick apply
Exton, PA · On-site
$125K - $161K/yr
Design, implement, and verify FPGA logic primarily targeting Xilinx FPGAs using Vivado * Develop RTL using Verilog and/or VHDL * Perform FPGA verification, including simulation, synthesis, timing ...
$125K - $161K/yr
Design, implement, and verify FPGA logic primarily targeting Xilinx FPGAs using Vivado * Develop RTL using Verilog and/or VHDL * Perform FPGA verification, including simulation, synthesis, timing ...
$125K - $161K/yr
Design, implement, and verify FPGA logic primarily targeting Xilinx FPGAs using Vivado * Develop RTL using Verilog and/or VHDL * Perform FPGA verification, including simulation, synthesis, timing ...
Exton, PA · On-site
$125K - $161K/yr
Design, implement, and verify FPGA logic primarily targeting Xilinx FPGAs using Vivado * Develop RTL using Verilog and/or VHDL * Perform FPGA verification, including simulation, synthesis, timing ...
Exton, PA · On-site
$125K - $161K/yr
Design, implement, and verify FPGA logic primarily targeting Xilinx FPGAs using Vivado * Develop RTL using Verilog and/or VHDL * Perform FPGA verification, including simulation, synthesis, timing ...
Allentown, PA · On-site
$134K - $163K/yr
Role- Design verification Engineer Location - Allentown, PA Duration - Full-time Visa Status - US ... stages like RTL,GLS releases. • Integrate System Verilog, OVM Test bench components like ...
Allentown, PA · On-site
$134K - $163K/yr
Role- Design verification Engineer Location - Allentown, PA Duration - Full-time Visa Status - US ... stages like RTL,GLS releases. • Integrate System Verilog, OVM Test bench components like ...
Allentown, PA · On-site
$134K/yr
... RTL design and verification Proven expertise in defining block and sub-system level test plans ... Bachelor in Electrical Engineering, Computer Science or related degree and 12+ years of proven ...
Allentown, PA · On-site
$134K/yr
... RTL design and verification Proven expertise in defining block and sub-system level test plans ... Bachelor in Electrical Engineering, Computer Science or related degree and 12+ years of proven ...
Austin, PA · On-site
$184K - $280K/yr
Engage with Engineering Directors to identify gaps in their RTL design, physical design (Place & Route), or post-silicon validation cycles. * Solution Architecture: Collaborate with Delivery Leads to ...
Austin, PA · On-site
$184K - $280K/yr
Engage with Engineering Directors to identify gaps in their RTL design, physical design (Place & Route), or post-silicon validation cycles. * Solution Architecture: Collaborate with Delivery Leads to ...
Bristol, PA · On-site
$102K - $139K/yr
... Engineer, Instrumentation Design Engineer to be a technical leader throughout the entire ... CPU / FPGA / GPU fabric, precision time distribution and discipline, and data interfaces. * Perform ...
Bristol, PA · On-site
$102K - $139K/yr
... Engineer, Instrumentation Design Engineer to be a technical leader throughout the entire ... CPU / FPGA / GPU fabric, precision time distribution and discipline, and data interfaces. * Perform ...
Bristol, PA · On-site
$102K - $139K/yr
... Engineer, Instrumentation Design Engineer to be a technical leader throughout the entire ... CPU / FPGA / GPU fabric, precision time distribution and discipline, and data interfaces. * Perform ...
Bristol, PA · On-site
$102K - $139K/yr
... Engineer, Instrumentation Design Engineer to be a technical leader throughout the entire ... CPU / FPGA / GPU fabric, precision time distribution and discipline, and data interfaces. * Perform ...
$126K - $162K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
$126K - $162K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
Bristol, PA · On-site
$102K - $139K/yr
... Engineer, Instrumentation Design Engineer to be a technical leader throughout the entire ... CPU / FPGA / GPU fabric, precision time distribution and discipline, and data interfaces. * Perform ...
Bristol, PA · On-site
$102K - $139K/yr
... Engineer, Instrumentation Design Engineer to be a technical leader throughout the entire ... CPU / FPGA / GPU fabric, precision time distribution and discipline, and data interfaces. * Perform ...
Bristol, PA · On-site
$102K - $139K/yr
... Engineer, Instrumentation Design Engineer to be a technical leader throughout the entire ... CPU / FPGA / GPU fabric, precision time distribution and discipline, and data interfaces. * Perform ...
Bristol, PA · On-site
$102K - $139K/yr
... Engineer, Instrumentation Design Engineer to be a technical leader throughout the entire ... CPU / FPGA / GPU fabric, precision time distribution and discipline, and data interfaces. * Perform ...
Design and integrate vector database solutions for efficient semantic search * Perform model ... Experience with CPU-based inference and optimization techniques * Practical experience with vector ...
Design and integrate vector database solutions for efficient semantic search * Perform model ... Experience with CPU-based inference and optimization techniques * Practical experience with vector ...
Philadelphia, PA · On-site
$80 - $150/hr
... Engineer Location: Philadelphia, PA Work Schedule: Hybrid 3 days on site, 2 remote Position ... Optimize CPU-based model inference through quantization and performance tuning. * Design and ...
Quick apply
Philadelphia, PA · On-site
$80 - $150/hr
... Engineer Location: Philadelphia, PA Work Schedule: Hybrid 3 days on site, 2 remote Position ... Optimize CPU-based model inference through quantization and performance tuning. * Design and ...
Canonsburg, PA · On-site
$101K/yr
Working across CPU and GPU architectures does not intimidate you. You have debugged MPI ... Design, implement, and optimize parallel programming methods within Ansys Mechanical solver ...
Canonsburg, PA · On-site
$101K/yr
Working across CPU and GPU architectures does not intimidate you. You have debugged MPI ... Design, implement, and optimize parallel programming methods within Ansys Mechanical solver ...
Pittsburgh, PA · On-site
$126K - $162K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
Pittsburgh, PA · On-site
$126K - $162K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
Canonsburg, PA · On-site
$101K - $151K/yr
Build and maintain software modules and subsystems that expose CPU- and GPU-based solver and post-processing capabilities in a multi-physics domain * Collaborate with other R&D engineers to design ...
Canonsburg, PA · On-site
$101K - $151K/yr
Build and maintain software modules and subsystems that expose CPU- and GPU-based solver and post-processing capabilities in a multi-physics domain * Collaborate with other R&D engineers to design ...
Canonsburg, PA · On-site
$112K - $148K/yr
... design and implement simulation features ... Responsibilities : • Build and maintain software modules and subsystems that expose CPU- and GPU ...
Canonsburg, PA · On-site
$112K - $148K/yr
... design and implement simulation features ... Responsibilities : • Build and maintain software modules and subsystems that expose CPU- and GPU ...
$40.6K - $51.4K
2% of jobs
$51.4K - $62.1K
11% of jobs
$67.8K is the 25th percentile. Wages below this are outliers.
$62.1K - $72.9K
23% of jobs
The median wage is $79.8K / yr.
$72.9K - $83.6K
22% of jobs
$83.6K - $94.4K
17% of jobs
$94.7K is the 75th percentile. Wages above this are outliers.
$94.4K - $105.1K
9% of jobs
$105.1K - $115.9K
6% of jobs
$115.9K - $126.6K
3% of jobs
$126.6K - $137.4K
3% of jobs
$137.4K - $148.1K
2% of jobs
$148.1K - $158.9K
1% of jobs
$40.6K
$88.4K
$158.9K
| Aspect | Cpu Rtl Design Engineer | Cpu Verification Engineer |
|---|---|---|
| Primary Focus | Designing and developing RTL code for CPU components | Verifying and testing RTL designs for correctness |
| Skills & Certifications | HDL languages (Verilog/VHDL), FPGA/ASIC design experience | HDL, testbench development, simulation tools |
| Work Environment | Design teams, hardware development labs | Verification teams, simulation environments |
| Industry Usage | Semiconductor companies, CPU design firms | ASIC/FPGA verification, chip validation |
While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

8.0
Based on 33 frontline employees who took The Breakroom Quiz
55th of 156 rated electronics manufacturers
Get the full story on Breakroom
Sourced by ZipRecruiter
It services
10,000+ Employees
Chandler, AZ, US
1989