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Cpu Rtl Design Engineer Jobs in Pennsylvania (NOW HIRING)

INNOVATIVE AEROSYSTEMS

FPGA Engineer

Exton, PA · On-site

$125K - $161K/yr

Design, implement, and verify FPGA logic primarily targeting Xilinx FPGAs using Vivado * Develop RTL using Verilog and/or VHDL * Perform FPGA verification, including simulation, synthesis, timing ...

Innovative Aerosystems

FPGA Engineer

Exton, PA · On-site

$125K - $161K/yr

Design, implement, and verify FPGA logic primarily targeting Xilinx FPGAs using Vivado * Develop RTL using Verilog and/or VHDL * Perform FPGA verification, including simulation, synthesis, timing ...

Innovative Solutions & Support

FPGA Engineer

Exton, PA · On-site

$125K - $161K/yr

Design, implement, and verify FPGA logic primarily targeting Xilinx FPGAs using Vivado * Develop RTL using Verilog and/or VHDL * Perform FPGA verification, including simulation, synthesis, timing ...

L3HHCM20

Senior Specialist, Systems Engineering

Bristol, PA · On-site

$102K - $139K/yr

... Engineer, Instrumentation Design Engineer to be a technical leader throughout the entire ... CPU / FPGA / GPU fabric, precision time distribution and discipline, and data interfaces. * Perform ...

EndoSec LLC

FPGA Engineer

Pittsburgh, PA · On-site

$126K - $162K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

EndoSec LLC

FPGA Engineer

Pittsburgh, PA · On-site

$126K - $162K/yr

Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

Arista Networks

Kernel software engineers are also responsible for the CPU subsystems on all Arista products. You ... Ability to design a solution and implement it successfully. Additional Information This role is a ...

Synopsys Inc

HPC Software Engineer

Canonsburg, PA · On-site

The HPC Software Engineer will design, implement, and optimize parallel programming methods within ... across CPU and GPU architectures using tools like Intel VTune, NVIDIA Nsight, or similar, and ...

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All JobsCpu Rtl Design Engineer JobsCpu Rtl Design Engineer Jobs in Pennsylvania

Cpu Rtl Design Engineer information

See Pennsylvania salary details

$40.6K

$88.4K

$158.9K

How much do cpu rtl design engineer jobs pay per year?

As of Jul 13, 2026, the average yearly pay for cpu rtl design engineer in Pennsylvania is $88,361.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,200.00 and $98,700.00 per year, depending on experience, location, and employer.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are CPU RTL Design Engineers?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
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Cpu Rtl Design Engineer jobs near you

ASIC/FPGA Design Engineer IV with Security Clearance

Global Edge Group, LLC

King Of Prussia, PA • On-site

$124K - $220K/yr

Other

Re-posted 24 days ago

Job description

The Global Edge Consultants, LLC is an Equal Opportunity Employer. The Global Edge Consultants, LLC does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need. Job Title: ASIC/FPGA Design Engineer IV – TS/SCI Clearance
Location: Boulder, CO; King of Prussia, PA; Littleton, CO; Louisville, CO; Sunnyvale, CA
Type of Role: Direct Hire (Full-Time, Onsite)
Shift: 9x80 Schedule (Every other Friday off)
Pay: Approximately $124,800 – $220,000/year POSITION OVERVIEW:
We are seeking an experienced ASIC/FPGA Design Engineer IV to support advanced space and national security programs within a highly classified aerospace and defense environment. This role is responsible for supporting FPGA and ASIC design, development, integration, and verification efforts for mission-critical space systems and secure hardware architectures. The ideal candidate has strong experience with FPGA/ASIC development methodologies, HDL programming, hardware integration, and cross-functional engineering collaboration supporting highly complex aerospace and defense initiatives. RESPONSIBILITIES AND ESSENTIAL DUTIES:
• Support FPGA and ASIC design, development, integration, and verification activities for advanced aerospace and defense systems
• Develop and implement FPGA/ASIC architectures supporting mission-critical space and national security applications
• Perform RTL design and development utilizing VHDL, Verilog, and/or SystemVerilog
• Support hardware integration, simulation, testing, debugging, and validation efforts
• Collaborate closely with systems engineering, hardware engineering, software engineering, and verification teams
• Support full FPGA/ASIC lifecycle execution including requirements, architecture, design, implementation, integration, and test
• Participate in design reviews, technical assessments, and engineering documentation activities
• Support timing analysis, synthesis, and hardware optimization efforts
• Utilize FPGA/ASIC development toolchains and simulation environments supporting complex hardware systems
• Support troubleshooting and root-cause analysis for hardware and system integration issues
• Participate in Agile and cross-functional engineering execution environments
• Support mission-critical national security and space system development efforts within highly classified environments MINIMUM REQUIREMENTS:
Basic Qualifications
• Experience with FPGA and/or ASIC design and development methodologies
• Experience programming utilizing VHDL, Verilog, and/or SystemVerilog
• Experience supporting hardware integration, simulation, and testing activities
• Familiarity with FPGA/ASIC toolchains and hardware development environments
• Ability to collaborate effectively within cross-functional engineering teams
• Active Top Secret Clearance required
• Ability to obtain and maintain TS/SCI eligibility
• U.S. Citizenship required Additional Qualifications
• Experience with FPGA synthesis, timing analysis, and hardware optimization
• Experience supporting mission-critical aerospace, defense, or national security systems
• Familiarity with ASIC verification and validation methodologies
• Experience with embedded hardware systems and high-reliability architectures preferred
• Strong troubleshooting and hardware debugging capabilities
• Experience supporting Agile engineering and collaborative development environments
• Excellent communication and technical documentation skills
• Experience supporting highly classified space or defense programs preferred The Global Edge Consultants, LLC is an Equal Opportunity Employer. The Global Edge Consultants, LLC does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need.

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