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Cpu Rtl Design Engineer Jobs in Ohio (NOW HIRING)

ComResource

Senior Elixir Engineer

Cincinnati, OH

$100.30K - $137.70K/yr

Diagnose CPU, I/O, and memory bottlenecks * Optimize BEAM scheduling, concurrency, and system ... Establish design patterns and architectural standards * Improve testing strategy, coverage, and ...

ComResource

Senior Elixir Engineer

Cincinnati, OH

$100.30K - $137.80K/yr

Own application performance and runtime behavior under production load Diagnose CPU, I/O, and ... design patterns and architectural standards Improve testing strategy, coverage, and release ...

EndoSec LLC

FPGA Engineer

Cincinnati, OH

$124.90K - $160.40K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

EndoSec LLC

FPGA Engineer

Cincinnati, OH · On-site

$124.70K - $160.20K/yr

Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

Booz Allen Hamilton

FPGA Developer

Beavercreek, OH

$99K - $225K/yr

... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...

Booz Allen Hamilton, Inc.

FPGA Developer

Beavercreek, OH · On-site

$99K - $225K/yr

... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...

Booz Allen Hamilton, Inc.

FPGA Developer

Beavercreek, OH · On-site

$99K - $225K/yr

... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...

LB Foster

Software Engineering Manager

Dublin, OH · On-site

... design standards, and delivery across a multi-layered Linux-based system. Responsible for release ... CPU architectures preferred. • Experience with hierarchical multi-level Linux-based product ...

KBR, Inc.

C++ Programmer

Beavercreek, OH · On-site

Program Summary KBR is searching for an experienced C++ Programmer to study, design, prepare ... Keen insight into data structures & algorithms, network stack (CPU, NIC, PCIe, and related drivers ...

Woolpert

SUE Crew Chief - Expression of Interest

Columbus, OH · On-site

$18.50 - $24.25/hr

... engineering, and geospatial services. We blend design excellence with cutting-edge technology to ... CPU literate: Basic computer skills, including familiarity with data transfer and basic software ...

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Cpu Rtl Design Engineer information

See Ohio salary details

$38.5K

$83.8K

$150.7K

How much do cpu rtl design engineer jobs pay per year?

As of May 29, 2026, the average yearly pay for cpu rtl design engineer in Ohio is $83,803.00, according to ZipRecruiter salary data. Most workers in this role earn between $64,600.00 and $93,600.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are CPU RTL Design Engineers?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are popular job titles related to Cpu Rtl Design Engineer jobs in Ohio? For Cpu Rtl Design Engineer jobs in Ohio, the most frequently searched job titles are:
What job categories do people searching Cpu Rtl Design Engineer jobs in Ohio look for? The top searched job categories for Cpu Rtl Design Engineer jobs in Ohio are:
What cities in Ohio are hiring for Cpu Rtl Design Engineer jobs? Cities in Ohio with the most Cpu Rtl Design Engineer job openings:
Cpu Rtl Design Engineer jobs near you
Infographic showing various Cpu Rtl Design Engineer job openings in Ohio as of May 2026, with employment types broken down into 1% As Needed, 3% Full Time, 67% Part Time, and 29% Contract. Highlights an 95% Physical, and 5% Remote job distribution, with an average salary of $83,803 per year, or $40.3 per hour.
Programmable Logic Design Engineer

Programmable Logic Design Engineer

Viasat, Inc.

Independence, OH • On-site

$193.50K - $290.50K/yr

Contractor

Posted 29 days ago

Viasat rating

3.4

Company rating: 3.4 out of 10

Based on 6 frontline employees who took The Breakroom Quiz

76th of 76 rated telecommunications companies

Job description

About us

One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.


What you'll do

In this role you will help develop high speed signal processing algorithms and/or network protocols in FPGAs. The individual will be responsible for the full design phase starting from the requirements' phase to documentation, block diagrams, implementation of source code, simulation, place & route, testing in hardware, and integration.


The day-to-day
  • Collaborate with team members to jointly develop high-speed digital signal processing and waveform processing algorithms supporting satellite communications applications
  • Develop testbenches and help maintain and update system level verification environment
  • Synthesize Verilog and System Verilog for Xilinx/AMD FPGAs
  • Develop timing constraints, analyze timing results, and implement design changes required to close timing
  • Generate and collaborate on required design documents, development requirements, specifications and verification protocols
  • Responsible for owning and driving technical issues to resolution
  • Integrate and debugs design in the laboratory

What you'll need
  • Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
  • 5-8 years FPGA design experience, including Xilinx Vivado
  • Strong knowledge of System Verilog
  • Experience with RTL design for various signal processing blocks, including but not limited to equalizers, correlators, filters, FEC encoders and decoders
  • Proven track record to design and implement FPGA modules using System Verilog with simulation and testbench development
  • Work independently, take initiative, and take ownership of tasks and results
  • Strong written and verbal communication skills, ability to work with a geographically distributed team

What will help you on the job
  • Familiarity with Matlab
  • Experience with GitHub
  • Experience with developing code for legacy Viasat modem platforms
  • Familiarity with DVB-S2x and DVB-RCS2 standards
  • Understanding and knowledge of Satellite communication waveforms and standards

#LI-BBS


Salary range
$155,500.00 - $246,000.00 / annually.For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $193,500.00- $290,500.00/ annually
At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat's comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.
EEO Statement

Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click here.

Qualifications:
  • Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
  • 5-8 years FPGA design experience, including Xilinx Vivado
  • Strong knowledge of System Verilog
  • Experience with RTL design for various signal processing blocks, including but not limited to equalizers, correlators, filters, FEC encoders and decoders
  • Proven track record to design and implement FPGA modules using System Verilog with simulation and testbench development
  • Work independently, take initiative, and take ownership of tasks and results
  • Strong written and verbal communication skills, ability to work with a geographically distributed team
Education:UNAVAILABLEEmployment Type: CONTRACTOR
ViaSat logo

About ViaSat

Sourced by ZipRecruiter

At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate.

Industry

Telecommunications

Company size

5,001 - 10,000 Employees

Headquarters location

Carlsbad, CA, US

Year founded

1986

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