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Cpu Rtl Design Engineer Jobs in Georgia (NOW HIRING)

Senior Software/Data Engineer

Atlanta, GA · Hybrid

$116K - $153K/yr

Design and scale fault-tolerant systems that balance consistency and availability. * Database ... Proactively identify bottlenecks by analyzing memory, CPU, and network usage. You will implement ...

Design and scale fault-tolerant systems that balance consistency and availability. * Database ... Proactively identify bottlenecks by analyzing memory, CPU, and network usage. You will implement ...

... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...

Staff Engineer

Atlanta, GA · On-site +1

$164K - $274K/yr

Design and implement scalable, high-performance backend systems using Go , with a strong focus on ... Drive performance optimization initiatives across services (CPU, memory, I/O, network), and ...

... CPU Refreshes etc... * Need to support inherited client automation code, implement & support ... Responsible for all automation tool functionality, design, integration, and implementation.

Senior Software Engineer

Alpharetta, GA · On-site

$85.90 - $137/hr

Design embedded software in C running on Linux to configure ASIC and hardware components ... Ability to interpret CPU hardware architectures, hardware functional specifications, and hardware ...

Staff Engineer

Atlanta, GA · On-site

$164K - $274K/yr

Design and implement scalable, high-performance backend systems using Go , with a strong focus on ... Drive performance optimization initiatives across services (CPU, memory, I/O, network), and ...

Senior Software Engineer - SRE

Atlanta, GA

$54.75 - $72.75/hr

Design and instrument SLIs such as latency, error rates, and availability across critical services ... These factors include database performance, network performance, CPU utilization, JVM tuning ...

Senior Software Engineer - SRE

Atlanta, GA · On-site

$54.75 - $72.75/hr

Design and instrument SLIs such as latency, error rates, and availability across critical services ... These factors include database performance, network performance, CPU utilization, JVM tuning ...

Senior AI Engineer

Atlanta, GA · On-site

$100K - $138K/yr

We are hiring a Senior AI Engineer to design, build, and operate enterprise AI systems across our ... Strong server-platform skills including CPU/GPU topologies, PCIe, BMC management, BIOS/firmware ...

Senior Software Engineer

Atlanta, GA · On-site

$117K - $155K/yr

Design embedded software in C running on Linux to configure ASIC and hardware components ... Ability to interpret CPU hardware architectures, hardware functional specifications, and hardware ...

Senior Software Engineer

Atlanta, GA · On-site +1

$117K - $155K/yr

Design embedded software in C running on Linux to configure ASIC and hardware components ... Ability to interpret CPU hardware architectures, hardware functional specifications, and hardware ...

Senior Software Engineer

Alpharetta, GA · On-site

$116K - $153K/yr

Design embedded software in C running on Linux to configure ASIC and hardware components ... Ability to interpret CPU hardware architectures, hardware functional specifications, and hardware ...

Senior Embedded Engineer

Atlanta, GA · On-site

$140 - $150/hr

Design, implement, and maintain firmware in C/C++ for bare‑metal microcontrollers and embedded ... Perform performance tuning and resource optimization (CPU, memory, power consumption) to meet ...

Senior Embedded Engineer

Atlanta, GA · Hybrid

$119K - $156K/yr

Design, implement, and maintain firmware in C/C++ for bare-metal microcontrollers and embedded ... Perform performance tuning and resource optimization (CPU, memory, power consumption) to meet ...

Senior Embedded Engineer

Atlanta, GA · On-site

$140K - $150K/yr

Design, implement, and maintain firmware in C/C++ for bare-metal microcontrollers and embedded ... Perform performance tuning and resource optimization (CPU, memory, power consumption) to meet ...

You can take defined design and turn it into code and deliver it on schedule, applying appropriate ... You are efficient with resource usage (e.g., system hardware, database, memory/CPU, infra costs)

Showing results 21-40

Cpu Rtl Design Engineer information

See Georgia salary details

$34.2K

$74.4K

$133.8K

How much do cpu rtl design engineer jobs pay per year?

As of Aug 10, 2026, the average yearly pay for cpu rtl design engineer in Georgia is $74,432.00, according to ZipRecruiter salary data. Most workers in this role earn between $57,400.00 and $83,200.00 per year, depending on experience, location, and employer.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What is a CPU RTL design engineer?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
What cities in Georgia are hiring for Cpu Rtl Design Engineer jobs? Cities in Georgia with the most Cpu Rtl Design Engineer job openings:
Infographic showing various Cpu Rtl Design Engineer job openings in Georgia as of August 2026, with employment types broken down into 1% Internship, 84% Full Time, 9% Part Time, 1% Temporary, and 5% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $74,432 per year, or $35.8 per hour.

Senior Software/Data Engineer

CINC

Atlanta, GA • Hybrid

$116K - $153K/yr

Full-time

Re-posted 6 days ago


Job description

Senior Software/Data Engineer


Role Overview

At CINC, we power the elite of real estate. As aSenior Software/Data Engineer on the TruBase platform, you will own the data transport, transformation, modeling, and analytics of real estate data points that drive institutional-grade insights for top-tier real estate professionals and organizations. We are looking for someone who understands software architecture design patterns and data modeling, including entity resolution at scale - building systems where data integrity is non-negotiable. The right candidate takes full ownership of their work, brings genuine curiosity to hard problems, and thrives as a highly skilled problem solver who can navigate ambiguity and drive solutions end-to-end.


Essential Responsibilities

  • Architect Distributed Systems: Design and scale fault-tolerant systems that balance consistency and availability.
  • Database Engineering: Evaluate and implement database technologies based on workload needs. You will own schema design, indexing strategies, and query optimization to ensure low-latency data access.
  • High-Throughput ETL/ELT: Build, monitor, and maintain "correct-by-design" pipelines. You'll ensure data integrity across the lifecycle of our high-volume data flows.
  • System Observability & Profiling: Proactively identify bottlenecks by analyzing memory, CPU, and network usage. You will implement distributed tracing and profiling to keep the system lean.
  • Technical Leadership: Drive innovation through Proof-of-Concepts (PoCs), document architectural decisions, and provide technical mentorship to junior engineers.


Technical Competencies & Experience

Core Requirements

  • Distributed Systems: Deep understanding of idempotence, consistency models, and consensus protocols.
  • Database Internals: Functional knowledge of storage engines (B+ Trees vs. LSM trees), storage formats (Columnar vs. Row), and tiering.
  • Performance Engineering: Proficiency in debugging and profiling tools (e.g., strace, py-spy, Flamegraphs) to optimize IO and CPU usage.
  • Data Streaming: Hands-on experience with log-based distributed systems such as Kafka, Pulsar, or Kinesis.
  • Modern Tooling: Strong Python skills and comfort with Kubernetes and CI/CD for data workflows. Experience with TypeScript is a plus.
  • Database Diversity: Familiarity with both relational and analytical stores (e.g., Postgres, Redshift, Clickhouse, DynamoDB).


Our Stack (what you'll work in day-to-day):
Python ClickHouse PostgreSQL Kafka Kubernetes


Preferred (Nice-to-Have)

  • Experience with lower-level languages (e.g., Rust, Go, or C++).
  • Deep understanding of serialization codecs and compression (Protobuf, FlatBuffers).
  • Knowledge of AWS Cloud Architecture and Data Governance frameworks.


How We Measure Success

  • System Reliability: Maintaining high uptime and scalability metrics under peak loads.
  • Performance Gains: Measurable improvements in query latency and pipeline throughput.
  • Architectural Integrity: Delivery of clean, well-documented code and system designs.
  • Team Growth: Positive impact on the technical growth and velocity of the broader engineering team.


Other Information:

  • Supervisory Responsibility: This position has no direct reports.
  • Reports to: VP of Data


Position Type/Expected Hours of Work

This is a full-time position; days and hours of work are Monday through Friday, 40 hours a week.
(Hybrid, Atlanta Area - 2 Days/Week in Office)


Work Authorization:Applicants must be legally authorized to work in the United States for any employer. We are unable to provide visa sponsorship (e.g., H-1B, OPT extensions) at this time.

This job description is not designed to cover or contain a comprehensive listing of activities, duties or responsibilities that are required of the employee for this job. Duties, responsibilities and activities may change at any time with or without notice.