As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro ... design to target power, performance, area and timing goals • Verification - support the ...
As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro ... design to target power, performance, area and timing goals • Verification - support the ...
As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro ... design to target power, performance, area and timing goals • Verification - support the ...
As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro ... design to target power, performance, area and timing goals • Verification - support the ...
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU MicroArchitect / RTL Engineer - Site Lead
Beaverton, OR · On-site
$106.60K - $140.50K/yr
Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that ... refinement of RTL design to target power, performance, area and timing goals • Validation ...
CPU MicroArchitect / RTL Engineer - Site Lead
Beaverton, OR · On-site
$106.60K - $140.50K/yr
Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that ... refinement of RTL design to target power, performance, area and timing goals • Validation ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Microarchitect/RTL Engineer - Execution, Load/Store Imagine what you could do here. At Apple ... Design delivery - work with multi-functional engineering team to implement and verify physical ...
CPU Microarchitect/RTL Engineer - Execution, Load/Store Imagine what you could do here. At Apple ... Design delivery - work with multi-functional engineering team to implement and verify physical ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU MicroArchitect / RTL Engineer - Site Lead
Beaverton, OR · On-site
$106.60K - $140.50K/yr
Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that ... refinement of RTL design to target power, performance, area and timing goals • Validation ...
CPU MicroArchitect / RTL Engineer - Site Lead
Beaverton, OR · On-site
$106.60K - $140.50K/yr
Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that ... refinement of RTL design to target power, performance, area and timing goals • Validation ...
CPU Power Management Microarchitect/RTL Engineer Work Locations (3) Submit Resume Imagine what you ... Design delivery - work with multi-functional engineering team to implement and verify physical ...
CPU Power Management Microarchitect/RTL Engineer Work Locations (3) Submit Resume Imagine what you ... Design delivery - work with multi-functional engineering team to implement and verify physical ...
Circuits Physical Design Engineer
Beaverton, OR · On-site
$141.50K - $145.70K/yr
... RTL to GDS steps. This will include physical synthesis, placement, CTS, routing, timing ... Familiar with ASIC integration flows, including power distribution, global signal planning, I/O ...
Circuits Physical Design Engineer
Beaverton, OR · On-site
$141.50K - $145.70K/yr
... RTL to GDS steps. This will include physical synthesis, placement, CTS, routing, timing ... Familiar with ASIC integration flows, including power distribution, global signal planning, I/O ...
Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science 7+ years of experience in RTL design and implementation for ASIC/SoC ...
Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science 7+ years of experience in RTL design and implementation for ASIC/SoC ...
CPU Power Management Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Power Management Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Power Management Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Power Management Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Power Management Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Power Management Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Power Management Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
CPU Power Management Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
Contractual Asic Rtl Design Engineer information
See Beaverton, OR salary details
$97.8K - $108K
16% of jobs
$108K - $118.2K
3% of jobs
$118.2K - $128.4K
4% of jobs
$131.4K is the 25th percentile. Wages below this are outliers.
$128.4K - $138.7K
6% of jobs
The median wage is $145.1K / yr.
$138.7K - $148.9K
33% of jobs
$148.9K - $159.1K
3% of jobs
$159.1K - $169.3K
2% of jobs
$176K is the 75th percentile. Wages above this are outliers.
$169.3K - $179.5K
12% of jobs
$179.5K - $189.7K
5% of jobs
$189.7K - $200K
4% of jobs
$200K - $210.2K
12% of jobs
$97.8K
$156.3K
$210.2K
How much do contractual asic rtl design engineer jobs pay per year?
As of May 28, 2026, the average yearly pay for contractual asic rtl design engineer in Beaverton, OR is $156,272.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,800.00 and $187,300.00 per year, depending on experience, location, and employer.
What is the difference between Contractual Asic Rtl Design Engineer vs Digital IC Design Engineer?
| Aspect | Contractual Asic Rtl Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Contract-based, project-specific, often in semiconductor or tech companies | Full-time or contract, working on digital integrated circuit design |
| Industry Usage | Common in semiconductor, electronics, and tech firms for ASIC development | Used across semiconductor, consumer electronics, and communication industries |
Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Beaverton, OR? The most popular types of Asic Rtl Design Engineer jobs in Beaverton, OR are:
What are popular job titles related to Contractual Asic Rtl Design Engineer jobs in Beaverton, OR? For Contractual Asic Rtl Design Engineer jobs in Beaverton, OR, the most frequently searched job titles are:
What job categories do people searching Contractual Asic Rtl Design Engineer jobs in Beaverton, OR look for? The top searched job categories for Contractual Asic Rtl Design Engineer jobs in Beaverton, OR are:
Apple rating
8.1
Based on 661 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! ..Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer who can drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems.
As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum BS and 10+ years of relevant industry experienceExperience with microprocessor architectureExperience with logic design principles with timing and power implicationsExperience in Verilog or VHDLExperience with simulators and waveform debugging process
Expertise in one or more of the following areas: coherence protocols and interconnects, high performance (low latency, high bandwidth) design techniques, memory subsystem queuing, scheduling, starvation and deadlock avoidance, SRAM design basics, multiple clock/power domains and power management strategies, prefetchers, replacement policies, debug capabilities, DFT strategies, error detection and correction Understanding of low power microarchitecture techniques Understanding of high-performance techniques and trade-offs in a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive language such as Perl or Python
As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum BS and 10+ years of relevant industry experienceExperience with microprocessor architectureExperience with logic design principles with timing and power implicationsExperience in Verilog or VHDLExperience with simulators and waveform debugging process
Expertise in one or more of the following areas: coherence protocols and interconnects, high performance (low latency, high bandwidth) design techniques, memory subsystem queuing, scheduling, starvation and deadlock avoidance, SRAM design basics, multiple clock/power domains and power management strategies, prefetchers, replacement policies, debug capabilities, DFT strategies, error detection and correction Understanding of low power microarchitecture techniques Understanding of high-performance techniques and trade-offs in a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive language such as Perl or Python
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976