Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Hillsboro, OR · On-site
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · On-site
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · On-site
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · On-site
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Beaverton, OR · On-site
$150 - $210/hr
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications * Experience writing specifications ...
Beaverton, OR · On-site
$150 - $210/hr
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications * Experience writing specifications ...
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
Hillsboro, OR · Hybrid
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hillsboro, OR · Hybrid
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hillsboro, OR · On-site
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hillsboro, OR · On-site
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hillsboro, OR · Hybrid
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hillsboro, OR · Hybrid
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
$129K - $194K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$129K - $194K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$129K - $194K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$129K - $194K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$150K - $277K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$150K - $277K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$150K - $277K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$150K - $277K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Beaverton, OR · On-site
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Beaverton, OR · On-site
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 5+ years of experience with RTL Design * Good English skills ...
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 5+ years of experience with RTL Design * Good English skills ...
$97.8K - $108K
16% of jobs
$108K - $118.2K
3% of jobs
$118.2K - $128.4K
4% of jobs
$131.4K is the 25th percentile. Wages below this are outliers.
$128.4K - $138.7K
6% of jobs
The median wage is $145.1K / yr.
$138.7K - $148.9K
33% of jobs
$148.9K - $159.1K
3% of jobs
$159.1K - $169.3K
2% of jobs
$176K is the 75th percentile. Wages above this are outliers.
$169.3K - $179.5K
12% of jobs
$179.5K - $189.7K
5% of jobs
$189.7K - $200K
4% of jobs
$200K - $210.2K
12% of jobs
$97.8K
$156.3K
$210.2K
| Aspect | Contractual Asic Rtl Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Contract-based, project-specific, often in semiconductor or tech companies | Full-time or contract, working on digital integrated circuit design |
| Industry Usage | Common in semiconductor, electronics, and tech firms for ASIC development | Used across semiconductor, consumer electronics, and communication industries |
Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.
$172K/yr
Full-time
Re-posted 18 hours ago
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Computer and electronic product manufacturing
10,000+ Employees
Cupertino, CA, US
1976
