Santa Clara, CA · On-site
$117K - $160K/yr
... EDA tool execution, distributed jobs, validation checks, and shared project state into observable ... Extend YAML/configuration systems to model workflow intent, stage contracts, validation markers ...
Santa Clara, CA · On-site
$117K - $160K/yr
... EDA tool execution, distributed jobs, validation checks, and shared project state into observable ... Extend YAML/configuration systems to model workflow intent, stage contracts, validation markers ...
Camden, NJ · On-site
$83.94/hr
Camden, New Jersey, 08103 Contract: 12 Months Contract to Hire ***Must have an active U.S ... Lead FPGA Engineer reporting to the Manager of Engineering (ASIC/FPGA), responsible for ...
Camden, NJ · On-site
$83.94/hr
Camden, New Jersey, 08103 Contract: 12 Months Contract to Hire ***Must have an active U.S ... Lead FPGA Engineer reporting to the Manager of Engineering (ASIC/FPGA), responsible for ...
Santa Clara, CA · On-site
$117K - $160K/yr
... EDA tool execution, distributed jobs, validation checks, and shared project state into observable ... Extend YAML/configuration systems to model workflow intent, stage contracts, validation markers ...
Santa Clara, CA · On-site
$117K - $160K/yr
... EDA tool execution, distributed jobs, validation checks, and shared project state into observable ... Extend YAML/configuration systems to model workflow intent, stage contracts, validation markers ...
Clarksville, MD · On-site
$122K - $161K/yr
This position is contingent upon contract award Markesman Group is seeking Hardware Engineers to ... The use of HII proprietary tools, FPGA vendor tools, and third-party EDA tools will be necessary to ...
Clarksville, MD · On-site
$122K - $161K/yr
This position is contingent upon contract award Markesman Group is seeking Hardware Engineers to ... The use of HII proprietary tools, FPGA vendor tools, and third-party EDA tools will be necessary to ...
Tucson, AZ · On-site
$46.52/hr
Contract Length: 12 months *Candidates must have an Active Secret Clearance to be considered for ... Experience using Mentor Graphics (Siemens EDA), PCB electronic circuit design software: HyperLynx ...
Tucson, AZ · On-site
$46.52/hr
Contract Length: 12 months *Candidates must have an Active Secret Clearance to be considered for ... Experience using Mentor Graphics (Siemens EDA), PCB electronic circuit design software: HyperLynx ...
Cloud Web Developer Position Overview This position supports United States Southern Command (USSOUTHCOM) under the Enhanced Domain Awareness (EDA) contract. The EDA team is refining the processes ...
New
Cloud Web Developer Position Overview This position supports United States Southern Command (USSOUTHCOM) under the Enhanced Domain Awareness (EDA) contract. The EDA team is refining the processes ...
New
Santa Clara, CA · On-site
$50 - $55/hr
Contract Work Arrangement: Onsite Number of Openings: 9 & Skill Requirement Required Skills ... Experience with industry-standard DFT/ATPG EDA tools. Ability to work effectively in fast-paced ...
Quick apply
Santa Clara, CA · On-site
$50 - $55/hr
Contract Work Arrangement: Onsite Number of Openings: 9 & Skill Requirement Required Skills ... Experience with industry-standard DFT/ATPG EDA tools. Ability to work effectively in fast-paced ...
Contract Interview: Phone/Skype Minimum 6+ years of experience in Analog and RF layout. Experience ... Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys. Experience ...
Contract Interview: Phone/Skype Minimum 6+ years of experience in Analog and RF layout. Experience ... Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys. Experience ...
Santa Clara, CA · On-site
$111K - $150K/yr
This role partners with Ampere's engineering, finance, and corporate functions to source, purchase ... Experience specifically engaging with EDA tools/software procurement and IP/licensing contract ...
Santa Clara, CA · On-site
$111K - $150K/yr
This role partners with Ampere's engineering, finance, and corporate functions to source, purchase ... Experience specifically engaging with EDA tools/software procurement and IP/licensing contract ...
Portland, OR · On-site
$100K - $136K/yr
This role partners with Ampere's engineering, finance, and corporate functions to source, purchase ... Experience specifically engaging with EDA tools/software procurement and IP/licensing contract ...
Portland, OR · On-site
$100K - $136K/yr
This role partners with Ampere's engineering, finance, and corporate functions to source, purchase ... Experience specifically engaging with EDA tools/software procurement and IP/licensing contract ...
Contract Interview: Phone/Skype • Minimum 6+ years of experience in Analog and RF layout. • ... standard EDA tools from Cadence, Mentor and Synopsys. • Experience with layout of high ...
Quick apply
Contract Interview: Phone/Skype • Minimum 6+ years of experience in Analog and RF layout. • ... standard EDA tools from Cadence, Mentor and Synopsys. • Experience with layout of high ...
Contract Interview: Phone/Skype • Minimum 6+ years of experience in Analog and RF layout. • ... standard EDA tools from Cadence, Mentor and Synopsys. • Experience with layout of high ...
Contract Interview: Phone/Skype • Minimum 6+ years of experience in Analog and RF layout. • ... standard EDA tools from Cadence, Mentor and Synopsys. • Experience with layout of high ...
San Jose, CA · On-site +1
$159K - $164K/yr
Title: Physical Design Engineer Location: 100% Remote Duration: Long Term Contract role ... Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus ...
San Jose, CA · On-site +1
$159K - $164K/yr
Title: Physical Design Engineer Location: 100% Remote Duration: Long Term Contract role ... Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus ...
Contract Project description The Principal Engineer, RTL Design within the NPU Hardware & Software ... Proficiency with EDA tools for synthesis, simulation, and timing analysis (Synopsys, Cadence ...
Contract Project description The Principal Engineer, RTL Design within the NPU Hardware & Software ... Proficiency with EDA tools for synthesis, simulation, and timing analysis (Synopsys, Cadence ...
San Jose, CA · On-site +1
$192K/yr
Contract Experience Required: * 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role ... Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools * Strong background in scan ...
San Jose, CA · On-site +1
$192K/yr
Contract Experience Required: * 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role ... Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools * Strong background in scan ...
ECAD SW Development Engineer (Contract Position) Job TitleECAD SW Development Engineer The Apple ... EDA vendor software - Cadence, Zuken, MentorExpertise in scripting languages - Cadence Skill, Perl ...
Quick apply
ECAD SW Development Engineer (Contract Position) Job TitleECAD SW Development Engineer The Apple ... EDA vendor software - Cadence, Zuken, MentorExpertise in scripting languages - Cadence Skill, Perl ...
$78K - $91K/yr
Position Summary We are seeking an Electronics Engineer to join our client's engineering team in ... EDA design tools. * Experience working in an Electronics Manufacturing Services (EMS) or contract ...
Quick apply
$78K - $91K/yr
Position Summary We are seeking an Electronics Engineer to join our client's engineering team in ... EDA design tools. * Experience working in an Electronics Manufacturing Services (EMS) or contract ...
*This position is contingent upon contract award Markesman Group is seeking Software Engineers to ... Vivado, ISE), embedded system design, EDA tools (synthesis, P&R, simulation), and/or ...
*This position is contingent upon contract award Markesman Group is seeking Software Engineers to ... Vivado, ISE), embedded system design, EDA tools (synthesis, P&R, simulation), and/or ...
Camden, NJ · On-site
$123K - $170K/yr
Chipton-Ross is seeking an FPGA/ASIC Design Engineer for a contract opportunity in Camden, NJ ... Mentor EDA CDC/Lint/AC/RDC POSITION RESPONSIBILITIES The FPGA/ASIC Design Engineer will be ...
Camden, NJ · On-site
$123K - $170K/yr
Chipton-Ross is seeking an FPGA/ASIC Design Engineer for a contract opportunity in Camden, NJ ... Mentor EDA CDC/Lint/AC/RDC POSITION RESPONSIBILITIES The FPGA/ASIC Design Engineer will be ...
*This position is contingent upon contract award Markesman Group is seeking Software Engineers to ... Vivado, ISE), embedded system design, EDA tools (synthesis, P&R, simulation), and/or ...
*This position is contingent upon contract award Markesman Group is seeking Software Engineers to ... Vivado, ISE), embedded system design, EDA tools (synthesis, P&R, simulation), and/or ...
$30.05 - $36.32
6% of jobs
$40.66 is the 25th percentile. Wages below this are outliers.
$36.32 - $42.59
27% of jobs
The median wage is $45.54 / hr.
$42.59 - $48.86
35% of jobs
$50.26 is the 75th percentile. Wages above this are outliers.
$48.86 - $55.14
28% of jobs
$55.14 - $61.41
2% of jobs
$61.41 - $67.68
0% of jobs
$67.68 - $73.95
0% of jobs
$73.95 - $80.22
0% of jobs
$80.22 - $86.49
0% of jobs
$86.49 - $92.77
0% of jobs
$92.77 - $99.04
1% of jobs
$30
$48
$99
$117K - $160K/yr
Full-time
Re-posted 21 days ago
9.3
Based on 5 frontline employees who took The Breakroom Quiz
15th of 209 rated software companies
The VLSI Productivity and Infrastructure team supports 1000+ chip design engineers with strong automation and workflows necessary to create world-changing silicon. We are building the next generation of production semiconductor design-flow infrastructure: a control-plane-driven RTL-to-GDS platform that turns design intent, configuration, generated collateral, EDA tool execution, distributed jobs, validation checks, and shared project state into observable, repeatable implementation workflows.
This role is for a senior flow/platform engineer who can work across synthesis, physical design, timing, signoff, ECO, and hierarchical execution. If you can envision and evolve legacy Tcl/Make/Perl/YAML infrastructure into a cleaner, more structured system while keeping active projects running, this role is for you!
What You'll Be Doing:
Build and modernize production RTL-to-GDS flow infrastructure across synthesis, place-and-route, timing, signoff, ECO, and handoff workflows
Extend YAML/configuration systems to model workflow intent, stage contracts, validation markers, generated artifacts, override order, and backward-compatible project behavior
Improve Make, Perl, Tcl, Python, and related launch infrastructure for generated runsets, EDA tool setup, distributed execution, status tracking, and failure diagnosis
Build faster prelaunch and in-run checks for missing inputs, stale generated files, invalid hooks, broken environment setup, bad constraints, and inconsistent design state
Develop job-control and observability capabilities for hierarchical and internally launched workflows, including parent-child job attachment, logs, provenance, and structured status
Partner with design and CAD users to debug failures across EDA tools, Linux environments, shared filesystems, schedulers, generated collateral, and configuration layers
What We Need To See:
B.S. or M.S. in CS, EE, CE, or equivalent experience
12+ years building, modernizing, or operating production EDA, VLSI CAD, RTL-to-GDS, physical design, or large engineering workflow systems
Strong hands-on experience with RTL-to-GDS or implementation flows, including setup, generated collateral, tool launch, checks, timing/signoff handoff, and debug workflows
Strong Tcl and Make experience in real EDA automation environments, plus practical software engineering skill in Python, Perl, Go, or C++
Ability to reason about layered configuration, includes, overrides, variable expansion, generated outputs, validation state, and compatibility with older projects
Excellent Linux debugging fundamentals and a track record of improving legacy production systems without breaking active users
Ways To Stand Out From The Crowd:
Background with production flows using commercial synthesis, place-and-route, timing, extraction, DRC/LVS, power, or signoff tools
Experience designing workflow engines, runset generators, configuration systems, template-driven automation, or job-control infrastructure
Background with distributed schedulers and shared compute environments such as LSF, Slurm, Grid Engine, or similar systems
Experience with NFS-heavy shared filesystems, stale state, partial writes, generated input files, provenance tracking, and reproducibility issues
Experience building structured checks, validation markers, data-fidelity tracking, dependency tracing, observability, or better-tested legacy Tcl/Make/Perl replacements
With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 184,000 USD - 287,500 USD for Level 4, and 224,000 USD - 356,500 USD for Level 5.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Computer and electronic product manufacturing
10,000+ Employees
Santa Clara, CA, US
1993
