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Chip Random Test Verification Engineer Jobs (NOW HIRING)

Anodize

Lead SoC Verification Engineer

Los Altos, CA · On-site

$161K/yr

Lead SoC Verification Engineer Summary We're a well-funded, stealth startup building a next ... Full chip/Block level verification: Develop directed/constrained random/random test cases to fully ...

Anodize

Lead SoC Verification Engineer

Los Altos, CA

$161K/yr

Lead SoC Verification Engineer Summary We're a well-funded, stealth startup building a next ... Full chip/Block level verification: Develop directed/constrained random/random test cases to fully ...

Sivaltech

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Create and execute directed and constrained-random test cases. * Perform functional, code ... Verify complex IPs and SoCs at block, subsystem, and chip level. * Work closely with RTL designers ...

SambaNova

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

... engineers, and take ownership of verification plans from first draft through closure. The team ... chip subsystems * Develop directed and constrained-random tests to identify architectural and ...

Infoyogi LLC

Verification Engineer

Santa Clara, CA · On-site

$158K/yr

... chip and overall system. § Be responsible for carefully documenting and executing test plan(s ... random tests to be run during simulation. § Be expected to adopt the evolving verification ...

Jobtailor

Test Verification Engineer

Dayton, OH · On-site

Test experience with signal generators, oscilloscopes, and spectrum analyzers * Experience with DoD sensor and weapon system engineering, development, and requirements verification * Capable of ...

New

Socket.dev

GSoC Design Verification Engineer

San Diego, CA · On-site

$98K - $147K/yr

... Chip (SOC) designs through comprehensive verification processes. You will develop and implement ... Create directed and constrained-random test scenarios to validate functionality and architectural ...

Apple

GPU Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

... random tests. - Run simulations and debug design and environment issues. - Create functional ... block, subsystem and chip level engineers to ensure seamless verification flow. Minimum ...

SambaNova

Design Verification Engineer

San Jose, CA · On-site

$120K - $200K/yr

... engineers, and take ownership of verification plans from first draft through closure. The team ... chip subsystems * Develop directed and constrained-random tests to identify architectural and ...

EE Recruiters

Verification Engineer

Santa Clara, CA · On-site

$160K/yr

... chip tests & triaging failures. * Your collaborative approach will be necessary in driving the ... You should have a thorough understanding of the constrained random asic verification process ...

Apple

GPU Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

... random tests. - Run simulations and debug design and environment issues. - Create functional ... block, subsystem and chip level engineers to ensure seamless verification flow. Minimum ...

EE Recruiters

Verification Engineer

Santa Clara, CA · On-site

$160K/yr

... chip tests & triaging failures. * Your collaborative approach will be necessary in driving the ... You should have a thorough understanding of the constrained random asic verification process ...

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Chip Random Test Verification Engineer information

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$80K

$142.6K

$203.5K

How much do chip random test verification engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for chip random test verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is a chip random test verification engineer?

Chip Random Test Verification Engineers are professionals who design, develop, and execute randomized test scenarios to verify the functionality and reliability of semiconductor chips. They use advanced verification methodologies, such as constrained-random simulation and coverage-driven verification, to identify potential design flaws before fabrication. These engineers work closely with design teams to create testbenches, analyze test results, and ensure that the chip meets all specifications and quality standards. Their work is crucial in detecting subtle bugs that might not be found with deterministic testing, ultimately improving chip performance and reducing costly errors.

What are some common challenges faced by a chip random test verification engineer and how can they be addressed?

Chip Random Test Verification Engineers often encounter challenges such as debugging complex test failures, ensuring comprehensive coverage, and managing large volumes of simulation data. Debugging can be time-consuming due to the random nature of test failures, which may be difficult to reproduce. To address these issues, engineers typically use advanced verification tools, maintain detailed logs, and collaborate closely with design and software teams for root cause analysis. Regular knowledge sharing within the team and adopting systematic debugging methodologies can also help streamline the verification process.

What are the key skills and qualifications needed to thrive as a chip random test verification engineer, and why are they important?

To thrive as a Chip Random Test Verification Engineer, you need a solid background in digital design, verification methodologies, and programming languages like SystemVerilog or UVM, typically supported by a degree in electrical engineering or computer engineering. Familiarity with simulation tools (e.g., ModelSim, VCS), testbench creation, and scripting languages such as Python or Perl is essential. Strong analytical thinking, attention to detail, and communication skills help you effectively collaborate with design teams and debug complex issues. These skills and qualities ensure the reliability and functionality of semiconductor chips before production, reducing costly errors and ensuring quality.

What are popular job titles related to Chip Random Test Verification Engineer jobs?

For Chip Random Test Verification Engineer jobs, the most frequently searched job titles are:

Lead SoC Verification Engineer

Los Altos, CA • On-site

Anodize
Motor Vehicle Manufacturing • 11 - 50 employees
Learn more about Anodizeexternal

$161K/yr

Full-time

Re-posted 27 days ago

Job description

Lead SoC Verification Engineer
Summary
We're a well-funded, stealth startup building a next-generation, end-to-end computing platform powered by a custom, high-performance edge SoC on an advanced process node. By integrating flagship compute IP into an industry-leading design, we are building the optimized silicon foundation for our software platform from the ground up.
We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Verification Engineer, you will help establish the verification and validation methodology for our end product.
Responsibilities
  • Cross Functional reviews: Participate in microarchitecture and design reviews with the designers to better understand the design to help develop a comprehensive DV plan. Develop a detailed test bench and plan for the blocks you will be working on and have them reviewed with the design and SW teams.
  • DV infrastructure development: Develop scalable test benches and libraries for block level and full chip level verification. Ensure stimulus is portable across verification, emulation and ASIC platforms. Implement test harness to collect various coverage metrics and scoreboards to track progress through regressions.
  • Full chip/Block level verification: Develop directed/constrained random/random test cases to fully stress the design, and track discovered bugs.
  • System Validation: Work closely with the validation team to use an emulation platform for accelerated verification and SW/HW co development.

Minimum Requirements
  • 10+ years of experience in verifying complex ASICs.
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience.
  • Deep knowledge of industry-standard on-chip interconnect protocols (AMBA CHI/AXI/AXI-S/APB).
  • Fluent in System verilog/System-C and UVM.
  • Experience verifying designs with multiple power domains using UPF and industry standard tools.
  • Proven track record of taking products through first pass Silicon success.

Preferred Qualifications
  • Experience with verifying multi-media SOCs.
  • Experience working directly with Arm cores and subsystems.
  • Experience with modeling and performance validation.
  • Exposure to Silicon bring-up.

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