Chip Lead / ASIC Director
San Jose, CA · On-site
$180 - $220/hr
A successful candidate will work with senior silicon design engineers, architects, and ... Chip Definition and Feasibility - identify critical trade‑offs and architectural decisions
San Jose, CA · On-site
$180 - $220/hr
A successful candidate will work with senior silicon design engineers, architects, and ... Chip Definition and Feasibility - identify critical trade‑offs and architectural decisions
San Jose, CA · On-site
$180 - $220/hr
A successful candidate will work with senior silicon design engineers, architects, and ... Chip Definition and Feasibility - identify critical trade‑offs and architectural decisions
... so engineers can drive complex tasks and cut ramp time. * Push the limits of what's possible in chip design with models and research harnesses on top of open-source foundations and iterating fast ...
... so engineers can drive complex tasks and cut ramp time. * Push the limits of what's possible in chip design with models and research harnesses on top of open-source foundations and iterating fast ...
Mountain View, CA · On-site
$163 - $236/hr
Static Timing Analysis Engineer, Full Chip STA * link Copy link corporate_fare Google place Mountain View, CA, USA Mid Experience driving progress, solving problems, and mentoring more junior team ...
Mountain View, CA · On-site
$163 - $236/hr
Static Timing Analysis Engineer, Full Chip STA * link Copy link corporate_fare Google place Mountain View, CA, USA Mid Experience driving progress, solving problems, and mentoring more junior team ...
... so engineers can drive complex tasks and cut ramp time. * Push the limits of what's possible in chip design with models and research harnesses on top of open-source foundations and iterating fast ...
... so engineers can drive complex tasks and cut ramp time. * Push the limits of what's possible in chip design with models and research harnesses on top of open-source foundations and iterating fast ...
Saratoga, CA · On-site
$250K - $280K/yr
The company is in execution mode and has a world-class engineering team with decades of experience ... Position Overview We are seeking a hands-on ASIC Chip Design Lead to own chip design execution from ...
Saratoga, CA · On-site
$250K - $280K/yr
The company is in execution mode and has a world-class engineering team with decades of experience ... Position Overview We are seeking a hands-on ASIC Chip Design Lead to own chip design execution from ...
We are hiring a Chip Firmware Validation Engineer to help us build the next generation of photonic AI processors and interconnects. In this role, you will be responsible for developing and validating ...
We are hiring a Chip Firmware Validation Engineer to help us build the next generation of photonic AI processors and interconnects. In this role, you will be responsible for developing and validating ...
San Jose, CA · On-site
$217K/yr
Serve as Engineering's interface to Technical Marketing; ensuring the product meets customer needs and supports the required functions and usage modes * Define/identify new device specific ...
San Jose, CA · On-site
$217K/yr
Serve as Engineering's interface to Technical Marketing; ensuring the product meets customer needs and supports the required functions and usage modes * Define/identify new device specific ...
Serve as Engineering's interface to Technical Marketing; ensuring the product meets customer needs ... The Chip Lead engages and resolves the problem when some aspect of the program is not meeting its ...
Serve as Engineering's interface to Technical Marketing; ensuring the product meets customer needs ... The Chip Lead engages and resolves the problem when some aspect of the program is not meeting its ...
Santa Clara, CA · On-site
$152 - $241.50/hr
As a software engineer, you will craft highly efficient software to automate and facilitate chip design and verification processes. What You'll Be Doing: * Work as a team to build reliable, scalable ...
New
Santa Clara, CA · On-site
$152 - $241.50/hr
As a software engineer, you will craft highly efficient software to automate and facilitate chip design and verification processes. What You'll Be Doing: * Work as a team to build reliable, scalable ...
New
Palo Alto, CA · On-site
$175K - $280K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING ...
Palo Alto, CA · On-site
$175K - $280K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING ...
Palo Alto, CA · On-site
$175K - $280K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING ...
Palo Alto, CA · On-site
$175K - $280K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
Irvine, CA · On-site
$165K - $260K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING ...
Irvine, CA · On-site
$165K - $260K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING ...
Irvine, CA · On-site
$165K - $260K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING ...
Irvine, CA · On-site
$165K - $260K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING ...
San Jose, CA · On-site
$170K - $196K/yr
A leading chip and silicon IP provider is seeking a Principal Verification Engineer in San Jose, CA. This full-time hybrid role involves leading verification strategies and working alongside talented ...
San Jose, CA · On-site
$170K - $196K/yr
A leading chip and silicon IP provider is seeking a Principal Verification Engineer in San Jose, CA. This full-time hybrid role involves leading verification strategies and working alongside talented ...
Mountain View, CA · On-site
$160K/yr
Chip Packaging Engineer Location: Mountain View, CA (Day 1 Onsite) Experience level: 3 Years Candidate Roles and Responsibilities • 3 years' experience completing layouts of high pin count, multi ...
Mountain View, CA · On-site
$160K/yr
Chip Packaging Engineer Location: Mountain View, CA (Day 1 Onsite) Experience level: 3 Years Candidate Roles and Responsibilities • 3 years' experience completing layouts of high pin count, multi ...
Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. * 8 years of technical experience in silicon timing closure and chip integration. * Experience in ...
Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. * 8 years of technical experience in silicon timing closure and chip integration. * Experience in ...
San Jose, CA · On-site
Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and ... Anticipate challenges early, drive alignment across all engineering functions, ensuring risks ...
San Jose, CA · On-site
Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and ... Anticipate challenges early, drive alignment across all engineering functions, ensuring risks ...
Collaborate with technical leads to resolve complex engineering challenges. * Ensure adherence to ... chip development projects. * Proven track record of successfully leading multiple complex ASIC/SoC ...
Collaborate with technical leads to resolve complex engineering challenges. * Ensure adherence to ... chip development projects. * Proven track record of successfully leading multiple complex ASIC/SoC ...
$19.6K - $33.8K
19% of jobs
$40.6K is the 25th percentile. Wages below this are outliers.
$33.8K - $48K
13% of jobs
$48K - $62.2K
8% of jobs
$62.2K - $76.4K
8% of jobs
The median wage is $78.3K / yr.
$76.4K - $90.6K
12% of jobs
$90.6K - $104.8K
9% of jobs
$114.1K is the 75th percentile. Wages above this are outliers.
$104.8K - $119K
8% of jobs
$119K - $133.2K
7% of jobs
$133.2K - $147.4K
6% of jobs
$147.4K - $161.6K
5% of jobs
$161.6K - $175.8K
3% of jobs
$19.6K
$85.8K
$175.8K
| Aspect | Chip Engineer | Hardware Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields |
| Work Environment | Design labs, fabrication facilities, simulation software | Design labs, schematic tools, testing environments |
| Industry Usage | Semiconductor companies, electronics firms, tech companies | Electronics manufacturers, consumer device companies, aerospace |
| Common Search/Comparison | Yes | Yes |
Chip Engineers focus on designing and developing integrated circuits and chips, often working on the entire chip architecture. Hardware Design Engineers concentrate on creating detailed schematics and layouts for electronic hardware components, including circuit boards and systems. While both roles require similar educational backgrounds and work environments, Chip Engineers typically work more on the semiconductor level, whereas Hardware Design Engineers focus on the physical hardware implementation.
For Chip Engineer jobs in California, the most frequently searched job titles are:
The top searched job categories for Chip Engineer jobs in California are:
Cities in California with the most Chip Engineer job openings:

$180 - $220/hr
Other
Re-posted 20 days ago
8.6
Based on 13 frontline employees who took The Breakroom Quiz
27th of 159 rated electronics manufacturers
As ASIC Director – Chip Lead in our Product Development team, you will be responsible for providing technical leadership to one or more Adaptive & Embedded Computing Group (AECG) device programs. You will have sign‑off responsibility for the technical execution of device programs from conception and planning to release to manufacturing. Your leadership responsibilities will focus on problem solving in all aspects of the device development cycle including architecture, RTL, analog & custom design, design for test & manufacturing, verification, physical design & timing closure, physical verification, tape‑out and post‑silicon validation & qualification. When a problem does not clearly fall under the banner of one technical team or another it becomes the responsibility of the Chip Lead to bring expertise, experience and diplomacy together to coordinate a solution.
The PersonThis position requires a wide breadth of understanding of and experience with ASIC design and development. It also requires strong interpersonal skills to resolve issues between highly skilled and experienced engineering colleagues. A successful candidate will work with senior silicon design engineers, architects, and micro‑architects from a wide variety of technical teams. The candidate will be attuned to the overall goals and objectives of the program and employ excellent communication and problem‑solving skills.
QualificationsThe Chip Lead works with one or more Program Managers. The Program Manager tracks that IP and chip development milestones and deliverables are achieved as scheduled. The Chip Lead engages and resolves the problem when some aspect of the program is not meeting its planned objectives. When engineering or marketing initiates a change to the program, the Chip Lead communicates the change and its consequences to all stakeholders.
This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Get the full story on Breakroom
Sourced by ZipRecruiter
Computer and electronic product manufacturing and manufacturing
5,001 - 10,000 Employees
Sunnyvale, CA, US