We are now looking for a Chip Engineering Operations Program Manager! The NVIDIA Engineering Operations group has an immediate opening for a top Program Manager. This group is responsible for the ...
We are now looking for a Chip Engineering Operations Program Manager! The NVIDIA Engineering Operations group has an immediate opening for a top Program Manager. This group is responsible for the ...
Chip Software Engineer
Sunnyvale, CA · On-site
$100 - $150/hr
Chip Software Engineer - Remote Bright Vision Technologies is a technology consulting and software development company delivering cloud, AI, data, and enterprise solutions across the United States.
Chip Software Engineer
Sunnyvale, CA · On-site
$100 - $150/hr
Chip Software Engineer - Remote Bright Vision Technologies is a technology consulting and software development company delivering cloud, AI, data, and enterprise solutions across the United States.
Chip Engineering Operations Program Manager
Santa Clara, CA · On-site
$136 - $259/hr
We are now looking for a Chip Engineering Operations Program Manager! The NVIDIA Engineering Operations group has an immediate opening for a top Program Manager. This group is responsible for the ...
Chip Engineering Operations Program Manager
Santa Clara, CA · On-site
$136 - $259/hr
We are now looking for a Chip Engineering Operations Program Manager! The NVIDIA Engineering Operations group has an immediate opening for a top Program Manager. This group is responsible for the ...
Senior Manager, ASIC Chip Engineering
Santa Clara, CA · On-site
$232 - $368/hr
... global engineering team.Provide technical leadership to the team.What we need to see:BSEE (MSEE / MSCE preferred) or equivalent experienceMinimum of 10 overall years of proven experience in chip ...
Senior Manager, ASIC Chip Engineering
Santa Clara, CA · On-site
$232 - $368/hr
... global engineering team.Provide technical leadership to the team.What we need to see:BSEE (MSEE / MSCE preferred) or equivalent experienceMinimum of 10 overall years of proven experience in chip ...
We are now looking for a Chip Engineering Operations Program Manager! The NVIDIA Engineering Operations group has an immediate opening for a top Program Manager. This group is responsible for the ...
We are now looking for a Chip Engineering Operations Program Manager! The NVIDIA Engineering Operations group has an immediate opening for a top Program Manager. This group is responsible for the ...
... engineering team. * Provide technical leadership to the team. What we need to see: * BSEE (MSEE / MSCE preferred) or equivalent experience * Minimum of 10 overall years of proven experience in chip ...
... engineering team. * Provide technical leadership to the team. What we need to see: * BSEE (MSEE / MSCE preferred) or equivalent experience * Minimum of 10 overall years of proven experience in chip ...
... engineering team. * Provide technical leadership to the team. What we need to see: * BSEE (MSEE / MSCE preferred) or equivalent experience * Minimum of 10 overall years of proven experience in chip ...
... engineering team. * Provide technical leadership to the team. What we need to see: * BSEE (MSEE / MSCE preferred) or equivalent experience * Minimum of 10 overall years of proven experience in chip ...
Packaging Engineer- Flip Chip
San Francisco, CA · On-site
$110 - $170/hr
We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). This spans bump ...
Packaging Engineer- Flip Chip
San Francisco, CA · On-site
$110 - $170/hr
We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). This spans bump ...
Chip Package Signal and Power Integrity Engineer
Sunnyvale, CA · On-site
$196K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 10 years of experience with SI/PI design for chip ...
Chip Package Signal and Power Integrity Engineer
Sunnyvale, CA · On-site
$196K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 10 years of experience with SI/PI design for chip ...
Software Engineer
Palo Alto, CA · On-site
Build and optimize our full-stack developer platform for chip engineers using TypeScript/JavaScript, Python and modern frameworks. * Integrate AI features in close collaboration with ML engineers ...
Software Engineer
Palo Alto, CA · On-site
Build and optimize our full-stack developer platform for chip engineers using TypeScript/JavaScript, Python and modern frameworks. * Integrate AI features in close collaboration with ML engineers ...
Software Engineer
Palo Alto, CA · On-site
$160K - $240K/yr
Build and optimize our full-stack developer platform for chip engineers using TypeScript/JavaScript, Python and modern frameworks. * Integrate AI features in close collaboration with ML engineers ...
Quick apply
Software Engineer
Palo Alto, CA · On-site
$160K - $240K/yr
Build and optimize our full-stack developer platform for chip engineers using TypeScript/JavaScript, Python and modern frameworks. * Integrate AI features in close collaboration with ML engineers ...
Chip Design and Verification Methodology Engineer
San Francisco, CA · On-site
$150 - $190/hr
Chip Design and Verification Methodology Engineer San Francisco Bay Area, CA · Hybrid · Full-time We are looking for a Chip Design and Verification Methodology Engineer who develops innovative ...
Chip Design and Verification Methodology Engineer
San Francisco, CA · On-site
$150 - $190/hr
Chip Design and Verification Methodology Engineer San Francisco Bay Area, CA · Hybrid · Full-time We are looking for a Chip Design and Verification Methodology Engineer who develops innovative ...
Physical Design Engineer - Full Chip Implementation
San Jose, CA · On-site
$190 - $270/hr
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs from synthesis through to GDSII ...
Physical Design Engineer - Full Chip Implementation
San Jose, CA · On-site
$190 - $270/hr
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs from synthesis through to GDSII ...
Physical Design Engineer - Full Chip Implementation
San Jose, CA · On-site
$180 - $240/hr
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs from synthesis through to GDSII ...
Physical Design Engineer - Full Chip Implementation
San Jose, CA · On-site
$180 - $240/hr
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs from synthesis through to GDSII ...
EDA Workflow Optimization Engineer
Santa Clara, CA · On-site
$130K - $154K/yr
As an engineer in our EDA Workflow Optimization team, you will partner closely with our engineering ... You will understand workflows covering the full chip design process from inception through study ...
EDA Workflow Optimization Engineer
Santa Clara, CA · On-site
$130K - $154K/yr
As an engineer in our EDA Workflow Optimization team, you will partner closely with our engineering ... You will understand workflows covering the full chip design process from inception through study ...
Senior Principal Engineer - Hardware Chip Lead, Connectivity BU
Santa Clara, CA · On-site
$130K - $174K/yr
Manage and communicate program status, risks, and mitigation plans to BU engineering leadership on a regular cadence Technical Leadership * Provide technical leadership for the full chip design ...
Senior Principal Engineer - Hardware Chip Lead, Connectivity BU
Santa Clara, CA · On-site
$130K - $174K/yr
Manage and communicate program status, risks, and mitigation plans to BU engineering leadership on a regular cadence Technical Leadership * Provide technical leadership for the full chip design ...
Senior Principal Engineer- SoC/Chip Lead
San Jose, CA · On-site
$350 - $520/hr
Lead cross-functional teams across digital design, verification, physical design, DFT, firmware, validation, packaging, and product engineering. * Define chip-level architecture, integration ...
Senior Principal Engineer- SoC/Chip Lead
San Jose, CA · On-site
$350 - $520/hr
Lead cross-functional teams across digital design, verification, physical design, DFT, firmware, validation, packaging, and product engineering. * Define chip-level architecture, integration ...
Lead cross-functional teams across digital design, verification, physical design, DFT, firmware, validation, packaging, and product engineering. * Define chip-level architecture, integration ...
Quick apply
Lead cross-functional teams across digital design, verification, physical design, DFT, firmware, validation, packaging, and product engineering. * Define chip-level architecture, integration ...
Physical Design Engineer - Full Chip Implementation
San Jose, CA · On-site
$200K - $300K/yr
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs--from synthesis through to GDSII ...
Quick apply
Physical Design Engineer - Full Chip Implementation
San Jose, CA · On-site
$200K - $300K/yr
As a top-level PD engineer, you will own full-chip implementation--encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs--from synthesis through to GDSII ...
Physical Design Engineer - Full Chip Implementation
San Jose, CA · On-site
$200K - $300K/yr
As a top-level PD engineer, you will own full-chip implementation-encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs-from synthesis through to GDSII ...
Physical Design Engineer - Full Chip Implementation
San Jose, CA · On-site
$200K - $300K/yr
As a top-level PD engineer, you will own full-chip implementation-encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs-from synthesis through to GDSII ...
Chip Engineer information
See California salary details
$19.6K - $33.8K
19% of jobs
$40.6K is the 25th percentile. Wages below this are outliers.
$33.8K - $48K
13% of jobs
$48K - $62.2K
8% of jobs
$62.2K - $76.4K
8% of jobs
The median wage is $78.3K / yr.
$76.4K - $90.6K
12% of jobs
$90.6K - $104.8K
9% of jobs
$114.1K is the 75th percentile. Wages above this are outliers.
$104.8K - $119K
8% of jobs
$119K - $133.2K
7% of jobs
$133.2K - $147.4K
6% of jobs
$147.4K - $161.6K
5% of jobs
$161.6K - $175.8K
3% of jobs
$19.6K
$85.8K
$175.8K
How much do chip engineer jobs pay per year?
What is a chip engineer?
What are the key skills and qualifications needed to thrive as a chip engineer?
What are some typical challenges a chip engineer faces when working on new semiconductor designs?
What is the difference between Chip Engineer vs Hardware Design Engineer?
| Aspect | Chip Engineer | Hardware Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields |
| Work Environment | Design labs, fabrication facilities, simulation software | Design labs, schematic tools, testing environments |
| Industry Usage | Semiconductor companies, electronics firms, tech companies | Electronics manufacturers, consumer device companies, aerospace |
| Common Search/Comparison | Yes | Yes |
Chip Engineers focus on designing and developing integrated circuits and chips, often working on the entire chip architecture. Hardware Design Engineers concentrate on creating detailed schematics and layouts for electronic hardware components, including circuit boards and systems. While both roles require similar educational backgrounds and work environments, Chip Engineers typically work more on the semiconductor level, whereas Hardware Design Engineers focus on the physical hardware implementation.
How do you become a chip engineer?
How much do chip engineers make?
What does a chip engineer do?
What are popular job titles related to Chip Engineer jobs in California?
For Chip Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Chip Engineer jobs in California look for?
The top searched job categories for Chip Engineer jobs in California are:
What cities in California are hiring for Chip Engineer jobs?
Cities in California with the most Chip Engineer job openings:

Chip Engineering Operations Program Manager
Santa Clara, CA • On-site
9.6
Based on 18 frontline employees who took The Breakroom Quiz
7th of 246 rated software companies
Great coworkers
People enjoy working here
Good employer
Respectful managers
Learn new skills
Full-time
Posted 15 days ago
Job description
We are now looking for a Chip Engineering Operations Program Manager! The NVIDIA Engineering Operations group has an immediate opening for a top Program Manager. This group is responsible for the silicon schedule from bring-up to production release. We are looking for individuals who thrive in a dynamic environment, and are not afraid to roll-up his their sleeves and get their hands dirty. We desire a self-starter, with great communication skills; as well as a leader, with a deep sense of commitment. You will be responsible for developing wafer forecasts, schedule generation and management, supporting cross-functional teams, and mitigating any programmatic risks. You will also review and improve processes, and handle prototype demand.
What you'll be doing:
- You own silicon bring-up schedule from power on to production release
- Negotiate silicon and board demand with teams and drive a bottom-up forecast
- Oversee and manage chip and board allocations across the company
- Lead prototype chip delivery to internal customers
- Track and coordinate engineering deliverables, key milestones and qualification/validation tasks in the new product introduction phase
- Identify and mitigate risks to schedules and programs
- Communicate status to cross-functional teams as well as upper management
- Continuously evaluate internal tools and processes and drive fixes to improve productivity
- Create new and fix existing processes between different teams
- Drive implementation of SW tools for data analytics and process evaluation
What we need to see:
- BS degree in Electrical or Computer Engineering or related (or equivalent experience)
- 5+ years in Semiconductor Program Management, ASIC Product Engineering, or ASIC design
- Deep understanding of ASIC Technology and Productization requirements
- Strong verbal and written communication skills, and the ability to coordinate with multiple technical and business teams
- Self-directed and driven, highly motivated, creative, and have a consistent record of handling multiple tasks at any given time
- Have the ability to work independently and follow complex procedures
- Proficient with MS Project and Excel
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 258,750 USD for Level 4.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until August 14, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993