This is a unique opportunity to grow your skills in infrastructure that supports chip development while working with world-class engineers across hardware, software, and operations disciplines. Key ...
This is a unique opportunity to grow your skills in infrastructure that supports chip development while working with world-class engineers across hardware, software, and operations disciplines. Key ...
This is a unique opportunity to grow your skills in infrastructure that supports chip development while working with world-class engineers across hardware, software, and operations disciplines. Key ...
New
This is a unique opportunity to grow your skills in infrastructure that supports chip development while working with world-class engineers across hardware, software, and operations disciplines. Key ...
New
Chip Design Engineer
Palo Alto, CA · On-site
We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... To close the loop between our AI and real silicon, we need an engineer who knows every step of the ...
Chip Design Engineer
Palo Alto, CA · On-site
We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... To close the loop between our AI and real silicon, we need an engineer who knows every step of the ...
Developed innovative chip design methodologies, EDA algorithms, design automation scripts, or ... You should be credible enough to engage directly with experienced customer engineering teams ...
Developed innovative chip design methodologies, EDA algorithms, design automation scripts, or ... You should be credible enough to engage directly with experienced customer engineering teams ...
Developed innovative chip design methodologies, EDA algorithms, design automation scripts, or ... You should be credible enough to engage directly with experienced customer engineering teams ...
Developed innovative chip design methodologies, EDA algorithms, design automation scripts, or ... You should be credible enough to engage directly with experienced customer engineering teams ...
Applied AI Engineer, Silicon Engineering
San Jose, CA · On-site
$2.0K/mo
Build, deploy, and maintain LLM-agent workflows that accelerate chip development: debug triage, testbench and coverage work, log/waveform analysis, EDA script generation, and engineering knowledge ...
Applied AI Engineer, Silicon Engineering
San Jose, CA · On-site
$2.0K/mo
Build, deploy, and maintain LLM-agent workflows that accelerate chip development: debug triage, testbench and coverage work, log/waveform analysis, EDA script generation, and engineering knowledge ...
Applied AI Engineer, Silicon Engineering
San Jose, CA · On-site
$2.0K/mo
Build, deploy, and maintain LLM‑agent workflows that accelerate chip development: debug triage, testbench and coverage work, log/waveform analysis, EDA script generation, and engineering knowledge ...
Applied AI Engineer, Silicon Engineering
San Jose, CA · On-site
$2.0K/mo
Build, deploy, and maintain LLM‑agent workflows that accelerate chip development: debug triage, testbench and coverage work, log/waveform analysis, EDA script generation, and engineering knowledge ...
Chip Lead / ASIC Director
San Jose, CA · On-site
The Role As ASIC Director - Chip Lead in our Product Development team, you will be responsible for ... A successful candidate will work with senior silicon design engineers, architects, and ...
Chip Lead / ASIC Director
San Jose, CA · On-site
The Role As ASIC Director - Chip Lead in our Product Development team, you will be responsible for ... A successful candidate will work with senior silicon design engineers, architects, and ...
HW/SW Codesign Engineer
San Francisco, CA · On-site
Today, chip development requires large teams, fragmented tools, and multi-year development cycles. We are building a closed-loop system in which models can reason about hardware, use engineering ...
HW/SW Codesign Engineer
San Francisco, CA · On-site
Today, chip development requires large teams, fragmented tools, and multi-year development cycles. We are building a closed-loop system in which models can reason about hardware, use engineering ...
... product engineering. * Define chip-level architecture, integration requirements, performance ... Drive issue resolution across the development lifecycle and ensure successful first-pass silicon ...
Quick apply
... product engineering. * Define chip-level architecture, integration requirements, performance ... Drive issue resolution across the development lifecycle and ensure successful first-pass silicon ...
Applied AI Engineer, Silicon Engineering
San Jose, CA · On-site
$150K - $275K/yr
Build, deploy, and maintain LLM-agent workflows that accelerate chip development: debug triage, testbench and coverage work, log/waveform analysis, EDA script generation, and engineering knowledge ...
Quick apply
Applied AI Engineer, Silicon Engineering
San Jose, CA · On-site
$150K - $275K/yr
Build, deploy, and maintain LLM-agent workflows that accelerate chip development: debug triage, testbench and coverage work, log/waveform analysis, EDA script generation, and engineering knowledge ...
Package Development Engineer
$150K - $249K/yr
Responsible for package architecture, substrate design, flip-chip integration, passive component ... Engineering, or related field. * 10+ years of semiconductor package development experience.
Package Development Engineer
$150K - $249K/yr
Responsible for package architecture, substrate design, flip-chip integration, passive component ... Engineering, or related field. * 10+ years of semiconductor package development experience.
Capture design decisions, lessons learned, and architectural rationale to accelerate follow-on chip development. What You BringRequired * BS, MS, or PhD in Electrical Engineering, Computer ...
Capture design decisions, lessons learned, and architectural rationale to accelerate follow-on chip development. What You BringRequired * BS, MS, or PhD in Electrical Engineering, Computer ...
Applied AI Engineer, Silicon Engineering
San Jose, CA · On-site
$150K - $275K/yr
Build, deploy, and maintain LLM-agent workflows that accelerate chip development: debug triage, testbench and coverage work, log/waveform analysis, EDA script generation, and engineering knowledge ...
Applied AI Engineer, Silicon Engineering
San Jose, CA · On-site
$150K - $275K/yr
Build, deploy, and maintain LLM-agent workflows that accelerate chip development: debug triage, testbench and coverage work, log/waveform analysis, EDA script generation, and engineering knowledge ...
Package Development Engineer
San Jose, CA · On-site
$150K - $249K/yr
Drive flip-chip integration, bump design, underfill selection, and assembly process optimization ... Engineering, or related field. * 10+ years of semiconductor package development experience.
Package Development Engineer
San Jose, CA · On-site
$150K - $249K/yr
Drive flip-chip integration, bump design, underfill selection, and assembly process optimization ... Engineering, or related field. * 10+ years of semiconductor package development experience.
Capture design decisions, lessons learned, and architectural rationale to accelerate follow-on chip development. What You Bring Required * BS, MS, or PhD in Electrical Engineering, Computer ...
Capture design decisions, lessons learned, and architectural rationale to accelerate follow-on chip development. What You Bring Required * BS, MS, or PhD in Electrical Engineering, Computer ...
Applied AI Engineer, Silicon Engineering
San Jose, CA · On-site
$2.0K/mo
Build, deploy, and maintain LLM‑agent workflows that accelerate chip development: debug triage, testbench and coverage work, log/waveform analysis, EDA script generation, and engineering knowledge ...
Applied AI Engineer, Silicon Engineering
San Jose, CA · On-site
$2.0K/mo
Build, deploy, and maintain LLM‑agent workflows that accelerate chip development: debug triage, testbench and coverage work, log/waveform analysis, EDA script generation, and engineering knowledge ...
RTL and Design Verification Engineer
Palo Alto, CA · On-site
$160K - $195K/yr
We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... We are hiring best‑in‑class engineers and researchers with real depth in RTL and design ...
RTL and Design Verification Engineer
Palo Alto, CA · On-site
$160K - $195K/yr
We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... We are hiring best‑in‑class engineers and researchers with real depth in RTL and design ...
... product engineering. * Define chip-level architecture, integration requirements, performance ... Drive issue resolution across the development lifecycle and ensure successful first-pass silicon ...
Quick apply
... product engineering. * Define chip-level architecture, integration requirements, performance ... Drive issue resolution across the development lifecycle and ensure successful first-pass silicon ...
RTL and Design Verification Engineer
Palo Alto, CA · On-site
$160K - $195K/yr
We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... We are hiring best‑in‑class engineers and researchers with real depth in RTL and design ...
RTL and Design Verification Engineer
Palo Alto, CA · On-site
$160K - $195K/yr
We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... We are hiring best‑in‑class engineers and researchers with real depth in RTL and design ...
Chip Development Engineer information
See salary details
$49K - $58.5K
3% of jobs
$58.5K - $68K
4% of jobs
$68K - $77.5K
16% of jobs
$78.4K is the 25th percentile. Wages below this are outliers.
$77.5K - $87K
19% of jobs
The median wage is $90.1K / yr.
$87K - $96.5K
24% of jobs
$103K is the 75th percentile. Wages above this are outliers.
$96.5K - $106K
13% of jobs
$106K - $115.5K
6% of jobs
$115.5K - $125K
5% of jobs
$125K - $134.5K
3% of jobs
$134.5K - $144K
5% of jobs
$144K - $153.5K
1% of jobs
$49K
$96.2K
$153.5K
How much do chip development engineer jobs pay per year?
What are popular job titles related to Chip Development Engineer jobs?
For Chip Development Engineer jobs, the most frequently searched job titles are:
Software Development Engineer - Silicon Development Infrastructure
Austin, TX • On-site
Full-time
Medical, Dental, Vision, Life, Retirement, PTO
Re-posted 15 days ago
Job description
infrastructure that accelerates silicon development at Annapurna Labs. In this role, you'll
contribute to the platforms, tooling, and automation that enable our chip design teams to iterate
faster, validate more thoroughly, and bring transformative silicon to market. You'll work at the
intersection of cloud infrastructure, high-performance computing, and electronic design
automation—building systems that directly impact AWS's ability to innovate in custom silicon.
This is a unique opportunity to grow your skills in infrastructure that supports chip development
while working with world-class engineers across hardware, software, and operations disciplines.
Key job responsibilities
Customer-Focused Infrastructure Development
• Partner with silicon design, verification, emulation, and software teams to understand
their development workflows, pain points, and iteration cycles.
• Build tooling and automation that eliminates manual toil and reduces time-to-results.
• Gather continuous feedback from internal customers and rapidly iterate on solutions.
Benchmark infrastructure based on silicon development workflows to provide internal
customers with the optimal resources for silicon development.
Own Platform Delivery and Operations
• Design, implement, and operate cloud infrastructure and high-performance computing
clusters using schedulers like Slurm.
• Build and maintain CI/CD pipelines for infrastructure-as-code and service deployments
with comprehensive testing and safe rollback mechanisms.
• Take ownership of platform reliability, performance, and cost efficiency from initial design
through production operation.
Drive Results Through Automation and Observability
• Develop monitoring, diagnostics, and alerting systems that surface actionable insights on
efficiency, utilization, reliability, and cost trends.
• Establish incident response processes, runbooks, and documentation that enable
operational excellence.
• Proactively anticipate system failures and implement preventive measures, reducing
operational toil and improving system resilience.
A day in the life
Each day you will work with some of the best engineers in the industry to develop Machine
Learning Accelerators. On-site in Austin, Texas, you will be part of the team that develops
custom silicon and contribute to the infrastructure that enables this innovation.
You might start your day investigating anomalies in job completion rates or resource utilization
patterns. You could spend your morning collaborating with a design verification team to optimize
their regression workflows, identifying bottlenecks and proposing improvements. In the
afternoon, you might be building new tooling that simplifies infrastructure access for emulation
teams, or contributing to monitoring dashboards that give teams real-time visibility into their
development velocity.
You'll participate in design reviews, contribute to postmortems when incidents occur, and
continuously refine the systems that accelerate the path from RTL to silicon. Throughout the
day, you'll balance immediate customer needs—unblocking a team waiting for compute capacity
—with longer-term platform investments. You'll write code, review infrastructure-as-code
changes, and collaborate across teams who depend on the systems you build.
Take a look inside our labs to see what you will learn at Annapurna Labs:
• https://www.aboutamazon.com/news/aws/take-a-look-inside-the-lab-where-aws-makes-
custom-chips
• https://youtu.be/rViVFrQg4Hk
About the team
At Annapurna Labs, your infrastructure work directly enables breakthrough innovations in
custom silicon that power AWS and transform industries. You'll collaborate with world-class chip
designers, verification engineers, and software developers who are pushing the boundaries of
what's possible. We offer the resources and scale of AWS with the innovation culture and
technical depth of a focused silicon team.
If you're passionate about building infrastructure that accelerates innovation, thrive on customer
obsession and ownership, and want to see your work enable the next generation of AWS silicon
—we want to hear from you
BASIC QUALIFICATIONS- 3+ years of non-internship professional software development experience
- 2+ years of non-internship design or architecture (design patterns, reliability and scaling) of new and existing systems experience
- Experience programming with at least one software programming language
- 2+ years of non-internship professional software development experience
- 2+ years of designing or architecting (design patterns, reliability and scaling) of new and existing systems experience
- 3+ years of administrative experience in networking, storage systems, operating systems and hands-on systems engineering experience
- Knowledge of systems engineering fundamentals (networking, storage, operating systems)
- Experience programming with at least one modern language such as C++, C#, Java,
- Python, Golang, PowerShell, Ruby
- Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent
PREFERRED QUALIFICATIONS- 3+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
- Bachelor's degree in computer science or equivalent
- Experience programming with at least one modern language such as Python, Ruby, Golang, Java, C++, C#, Rust with demonstrated ability to write production-quality, maintainable code
- • Experience utilizing AWS cloud solutions in a DevOps environment with infrastructure as code (CloudFormation, Terraform, CDK)
- • Experience with Linux/Unix
- • Experience in automating, deploying, and supporting large-scale infrastructure
- • Experience with high-performance computing (HPC) clusters using workload schedulers like Slurm
- • Familiarity with semiconductor development workflows or electronic design automation (EDA) environments
- • Experience building services using AWS products
- • Experience with CI/CD pipelines and build processes
- • Experience with monitoring, observability, and incident management at scale
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.
USA, TX, Austin - 143,700.00 - 194,400.00 USD annually