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Block Level Asic Soc Verification Engineer Jobs

Lead SoC Verification Engineer

Los Altos, CA ยท On-site

$161K/yr

... ASIC design house through the process. As our Lead SoC Verification Engineer, you will help ... Develop scalable test benches and libraries for block level and full chip level verification.

... ASIC design house through the process. As our Lead SoC Verification Engineer, you will help ... Develop scalable test benches and libraries for block level and full chip level verification.

Design Verification Engineer

San Diego, CA ยท On-site

$144K - $176K/yr

Develop and execute comprehensive verification plans for ASIC/SoC designs. * Build reusable UVM ... Verify complex IPs and SoCs at block, subsystem, and chip level. * Work closely with RTL designers ...

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Block Level Asic Soc Verification Engineer information

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$88K

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$207K

How much do block level asic soc verification engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for block level asic soc verification engineer in the United States is $156,077.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $175,500.00 per year, depending on experience, location, and employer.

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Infographic showing various Block Level Asic Soc Verification Engineer job openings in the United States as of June 2026, with employment types broken down into 1% As Needed, 97% Full Time, and 2% Part Time. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $156,077 per year, or $75 per hour.

Sr. Asic Design Verification Engineer

Austin, TX โ€ข On-site

VentureSoft Global
501 - 1,000 employees

$134K - $164K/yr

Other

Re-posted 17 days ago


Job description

Job Title: Senior ASIC Design Verification Engineer
Location: Austin, TX (Onsite/Hybrid)
Experience: 15+ Years
Job Summary
We are seeking an experienced Senior ASIC Design Verification Engineer to verify next-generation CPU, AI/ML, and SoC designs. The ideal candidate will have strong expertise in developing UVM-based verification environments, functional coverage, RTL debug, and constrained-random verification while working closely with design and architecture teams from specification through tape-out.
Primary Skills (Must Have)
  • SystemVerilog & UVM
  • Constrained Random Verification (CRV)
  • Functional Coverage & Coverage Closure
  • RTL Debug & ASIC/SoC Verification
Key Responsibilities
  • Develop UVM/SystemVerilog verification environments.
  • Create test plans, testbenches, sequences, scoreboards, and checkers.
  • Perform block-level and full-chip ASIC/SoC verification.
  • Execute constrained-random and directed testing.
  • Debug RTL issues and drive functional coverage closure.
  • Collaborate with design, architecture, and validation teams.
  • Support regression, verification signoff, and tape-out activities.
Preferred Skills
  • CPU/Processor or Memory Subsystem Verification
  • SVA (SystemVerilog Assertions)
  • ARM, RISC, AI/ML Accelerator, or GPU verification
  • Experience with VCS, Questa, or Xcelium
  • Python or C/C++
Education
Bachelor''s or Master''s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.