... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
Circuit Design Automation Engineer
Austin, TX · On-site
$172.10K - $305.60K/yr
... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...
Circuit Design Automation Engineer
Austin, TX · On-site
$172.10K - $305.60K/yr
... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...
Circuit Design Automation Engineer
Austin, TX · On-site
$172.10K - $305.60K/yr
... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...
Circuit Design Automation Engineer
Austin, TX · On-site
$172.10K - $305.60K/yr
... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...
Staff Engineer, SRAM Layout
San Jose, CA · On-site
Design and optimize SRAM layouts at the cell, array, and peripheral levels for area, speed, power ... Lead layout reviews, mentor junior engineers, and drive best practices, optimization techniques ...
Staff Engineer, SRAM Layout
San Jose, CA · On-site
Design and optimize SRAM layouts at the cell, array, and peripheral levels for area, speed, power ... Lead layout reviews, mentor junior engineers, and drive best practices, optimization techniques ...
Custom Circuits Design Engineer
$147.40K - $272.10K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Custom Circuits Design Engineer
$147.40K - $272.10K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Staff Engineer, SRAM Layout
San Jose, CA · On-site
Design and optimize SRAM layouts at the cell, array, and peripheral levels for area, speed, power ... Lead layout reviews, mentor junior engineers, and drive best practices, optimization techniques ...
Quick apply
Staff Engineer, SRAM Layout
San Jose, CA · On-site
Design and optimize SRAM layouts at the cell, array, and peripheral levels for area, speed, power ... Lead layout reviews, mentor junior engineers, and drive best practices, optimization techniques ...
... Engineering, Microelectronics, or related fields * 10+ years of hands-on SRAM memory compiler ... Support optimization, debug, and design-rule closure * Proficiency with Cadence Virtuoso and ...
... Engineering, Microelectronics, or related fields * 10+ years of hands-on SRAM memory compiler ... Support optimization, debug, and design-rule closure * Proficiency with Cadence Virtuoso and ...
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
Postdoctoral Fellow - ECE Y. Zhang
Charlotte, NC · On-site
$60K/yr
D in Electrical Engineering, Physics or related areas awarded within the last five years. * SRAM design, fabrication, and testing: Expertise in all areas is highly preferred * Design, fabrication ...
Postdoctoral Fellow - ECE Y. Zhang
Charlotte, NC · On-site
$60K/yr
D in Electrical Engineering, Physics or related areas awarded within the last five years. * SRAM design, fabrication, and testing: Expertise in all areas is highly preferred * Design, fabrication ...
Work closely with other engineering teams, such as analog and digital, to ensure seamless ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Work closely with other engineering teams, such as analog and digital, to ensure seamless ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Work closely with other engineering teams, such as analog and digital, to ensure seamless ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Work closely with other engineering teams, such as analog and digital, to ensure seamless ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Senior Design Engineer
Annapolis, MD · On-site
$135K - $230K/yr
As the Senior Design Engineer, you will develop, maintain and test high-performance FPGA computing ... Develop FPGA interfaces to SRAM/DRAM, Multi-Gigabit Transceivers, ADCs/DACs * Create example ...
Senior Design Engineer
Annapolis, MD · On-site
$135K - $230K/yr
As the Senior Design Engineer, you will develop, maintain and test high-performance FPGA computing ... Develop FPGA interfaces to SRAM/DRAM, Multi-Gigabit Transceivers, ADCs/DACs * Create example ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$147.40K - $272.10K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$147.40K - $272.10K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
Exposure to memory design (DRAM, NAND, SRAM) or high-speed circuit design * Experience with layout tools and physical design methodologies * Knowledge of scripting or programming (e.g., Python, TCL ...
Exposure to memory design (DRAM, NAND, SRAM) or high-speed circuit design * Experience with layout tools and physical design methodologies * Knowledge of scripting or programming (e.g., Python, TCL ...
DRAM Design Engineer
Boise, ID · On-site
Exposure to memory design (DRAM, NAND, SRAM) or high-speed circuit design * Experience with layout tools and physical design methodologies * Knowledge of scripting or programming (e.g., Python, TCL ...
DRAM Design Engineer
Boise, ID · On-site
Exposure to memory design (DRAM, NAND, SRAM) or high-speed circuit design * Experience with layout tools and physical design methodologies * Knowledge of scripting or programming (e.g., Python, TCL ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
Associate Sram Design Engineer information
See salary details
$41.5K - $49.7K
1% of jobs
$49.7K - $58K
6% of jobs
$58K - $66.2K
17% of jobs
$66.3K is the 25th percentile. Wages below this are outliers.
$66.2K - $74.4K
22% of jobs
The median wage is $76.1K / yr.
$74.4K - $82.6K
18% of jobs
$82.6K - $90.9K
10% of jobs
$91.5K is the 75th percentile. Wages above this are outliers.
$90.9K - $99.1K
10% of jobs
$99.1K - $107.3K
8% of jobs
$107.3K - $115.5K
4% of jobs
$115.5K - $123.8K
2% of jobs
$123.8K - $132K
2% of jobs
$41.5K
$82.6K
$132K
How much do associate sram design engineer jobs pay per year?
As of May 30, 2026, the average yearly pay for associate sram design engineer in the United States is $82,636.00, according to ZipRecruiter salary data. Most workers in this role earn between $65,500.00 and $95,000.00 per year, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive as an Associate SRAM Design Engineer, and why are they important?
To thrive as an Associate SRAM Design Engineer, you need a solid background in electrical engineering, CMOS circuit design, and semiconductor device physics, usually supported by a relevant degree. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), scripting languages, and possibly knowledge of Verilog or SPICE simulations is typically required. Strong problem-solving abilities, attention to detail, and effective teamwork are important soft skills in this role. These competencies are crucial to ensure accurate, reliable memory designs that meet performance, power, and area specifications in a collaborative engineering environment.
What are some common challenges an Associate SRAM Design Engineer may face when transitioning from academic projects to industry roles?
In transitioning from academia to an industry role as an Associate SRAM Design Engineer, you may encounter challenges such as adapting to strict project timelines, collaborating closely with cross-functional teams, and adhering to standardized design and verification flows. Unlike academic projects, industry work often requires balancing innovation with strict adherence to design specifications, power/performance constraints, and manufacturability. Additionally, you'll need to quickly become proficient with industry-standard EDA tools, scripting, and revision control systems, as well as participate in regular design reviews and debugging sessions with senior engineers.
What are Associate SRAM Design Engineers?
Associate SRAM Design Engineers are entry-level professionals who work on the design, development, and verification of Static Random Access Memory (SRAM) circuits, which are crucial components in microprocessors and various digital devices. They assist senior engineers in tasks such as circuit schematic design, layout, simulation, and testing to ensure optimal performance, power efficiency, and reliability of SRAM blocks. Their role often involves working with electronic design automation (EDA) tools and collaborating with cross-functional teams to deliver robust memory solutions. This position is ideal for individuals with a background in electrical or electronics engineering and a strong understanding of digital circuit design principles.
What is the difference between Associate Sram Design Engineer vs Memory Design Engineer?
| Aspect | Associate Sram Design Engineer | Memory Design Engineer |
|---|---|---|
| Credentials | Bachelor's in Electrical Engineering or related field; some roles may prefer a Master's | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related discipline |
| Work Environment | Design teams in semiconductor or electronics companies, focusing on SRAM architecture and circuit design | Memory development teams working on various types of memory, including SRAM, DRAM, and Flash |
| Industry Usage | Commonly used in semiconductor companies, consumer electronics, and hardware startups | Widely used across semiconductor, consumer electronics, and data storage industries |
While both roles involve memory technology and circuit design, an Associate Sram Design Engineer specializes specifically in SRAM architecture and design, whereas a Memory Design Engineer may work on a broader range of memory types. The Associate Sram Design Engineer typically focuses on SRAM-related projects within semiconductor companies, making it a more specialized position.
What cities are hiring for Associate Sram Design Engineer jobs? Cities with the most Associate Sram Design Engineer job openings:
What are the most commonly searched types of Sram Design Engineer jobs? The most popular types of Sram Design Engineer jobs are:
What states have the most Associate Sram Design Engineer jobs? States with the most job openings for Associate Sram Design Engineer jobs include:
Apple rating
8.1
Based on 661 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! ..Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer who can drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems.
As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum BS and 3+ years of relevant industry experienceExperience with microprocessor architectureExperience with logic design principles with timing and power implicationsExperience in Verilog or VHDLExperience with simulators and waveform debugging process
Expertise in one or more of the following areas: coherence protocols and interconnects, high performance (low latency, high bandwidth) design techniques, memory subsystem queuing, scheduling, starvation and deadlock avoidance, SRAM design basics, multiple clock/power domains and power management strategies, prefetchers, replacement policies, debug capabilities, DFT strategies, error detection and correction Understanding of low power microarchitecture techniques Understanding of high-performance techniques and trade-offs in a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive language such as Perl or Python
As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum BS and 3+ years of relevant industry experienceExperience with microprocessor architectureExperience with logic design principles with timing and power implicationsExperience in Verilog or VHDLExperience with simulators and waveform debugging process
Expertise in one or more of the following areas: coherence protocols and interconnects, high performance (low latency, high bandwidth) design techniques, memory subsystem queuing, scheduling, starvation and deadlock avoidance, SRAM design basics, multiple clock/power domains and power management strategies, prefetchers, replacement policies, debug capabilities, DFT strategies, error detection and correction Understanding of low power microarchitecture techniques Understanding of high-performance techniques and trade-offs in a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive language such as Perl or Python
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976