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Associate Sram Design Engineer Jobs (NOW HIRING)

Nvidia

Senior SRAM Layout Design Engineer

Austin, TX · Hybrid

Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...

Nvidia

Senior SRAM Layout Design Engineer

Durham, NC · Hybrid

Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...

7Rays Semiconductors

CA · On-site

... for SRAM and memory blocks, covering array layout, periphery positioning, power grid design ... engineers, and help raise layout quality and execution rigor across the team. Have a BSEE or ...

Resource Point LLC

Memory Design Engineer

Troy, MI · On-site

Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte Carlo Simulations. * Exposure to full embedded memory design flow: Architecture, circuit design, physical ...

Microsoft

Principal Circuit Design Engineer

Raleigh, NC · On-site

$188K - $304K/yr

Responsibilities * Collaborate with SoC designers to develop Memory SRAM and Register file ... design value propositions and risks. * Effective debug skills. #SCHIE Silicon Engineering IC5 - The ...

Apple

Custom Circuits Design Engineer

Beaverton, OR · On-site

We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...

Apple

Circuit Design Automation Engineer

Austin, TX · On-site

... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...

Apple

Circuit Design Automation Engineer

Austin, TX

$175K - $311K/yr

... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...

Apple

Circuit Design Automation Engineer

Austin, TX

$175K - $311K/yr

... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...

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Associate Sram Design Engineer information

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How much do associate sram design engineer jobs pay per year?

As of Jul 14, 2026, the average yearly pay for associate sram design engineer in the United States is $82,636.00, according to ZipRecruiter salary data. Most workers in this role earn between $65,500.00 and $95,000.00 per year, depending on experience, location, and employer.

What is the difference between Associate Sram Design Engineer vs Memory Design Engineer?

AspectAssociate Sram Design EngineerMemory Design Engineer
CredentialsBachelor's in Electrical Engineering or related field; some roles may prefer a Master'sBachelor's or Master's in Electrical Engineering, Computer Engineering, or related discipline
Work EnvironmentDesign teams in semiconductor or electronics companies, focusing on SRAM architecture and circuit designMemory development teams working on various types of memory, including SRAM, DRAM, and Flash
Industry UsageCommonly used in semiconductor companies, consumer electronics, and hardware startupsWidely used across semiconductor, consumer electronics, and data storage industries

While both roles involve memory technology and circuit design, an Associate Sram Design Engineer specializes specifically in SRAM architecture and design, whereas a Memory Design Engineer may work on a broader range of memory types. The Associate Sram Design Engineer typically focuses on SRAM-related projects within semiconductor companies, making it a more specialized position.

What are Associate SRAM Design Engineers?

Associate SRAM Design Engineers are entry-level professionals who work on the design, development, and verification of Static Random Access Memory (SRAM) circuits, which are crucial components in microprocessors and various digital devices. They assist senior engineers in tasks such as circuit schematic design, layout, simulation, and testing to ensure optimal performance, power efficiency, and reliability of SRAM blocks. Their role often involves working with electronic design automation (EDA) tools and collaborating with cross-functional teams to deliver robust memory solutions. This position is ideal for individuals with a background in electrical or electronics engineering and a strong understanding of digital circuit design principles.

What are the key skills and qualifications needed to thrive as an Associate SRAM Design Engineer, and why are they important?

To thrive as an Associate SRAM Design Engineer, you need a solid background in electrical engineering, CMOS circuit design, and semiconductor device physics, usually supported by a relevant degree. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), scripting languages, and possibly knowledge of Verilog or SPICE simulations is typically required. Strong problem-solving abilities, attention to detail, and effective teamwork are important soft skills in this role. These competencies are crucial to ensure accurate, reliable memory designs that meet performance, power, and area specifications in a collaborative engineering environment.

What are some common challenges an Associate SRAM Design Engineer may face when transitioning from academic projects to industry roles?

In transitioning from academia to an industry role as an Associate SRAM Design Engineer, you may encounter challenges such as adapting to strict project timelines, collaborating closely with cross-functional teams, and adhering to standardized design and verification flows. Unlike academic projects, industry work often requires balancing innovation with strict adherence to design specifications, power/performance constraints, and manufacturability. Additionally, you'll need to quickly become proficient with industry-standard EDA tools, scripting, and revision control systems, as well as participate in regular design reviews and debugging sessions with senior engineers.
What cities are hiring for Associate Sram Design Engineer jobs? Cities with the most Associate Sram Design Engineer job openings:
What are the most commonly searched types of Sram Design Engineer jobs? The most popular types of Sram Design Engineer jobs are:
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Associate Sram Design Engineer jobs near you
Senior SRAM Layout Design Engineer

Senior SRAM Layout Design Engineer

Nvidia Corporation

Santa Clara, CA • On-site

Full-time

Re-posted 2 days ago

Nvidia rating

9.3

Company rating: 9.3 out of 10

Based on 5 frontline employees who took The Breakroom Quiz

15th of 209 rated software companies

Job description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean tapeout, working closely with circuit design, physical design, integration, CAD, and foundry teams. This is a senior individual contributor role for someone who can produce complex layouts, make informed advanced-node tradeoffs, improve layout methodology, and guide junior engineers.
What you will be doing:
  • Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
  • Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
  • Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
  • Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
  • Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
  • Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
  • Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
  • Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
  • Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

What we need to see:
  • Have a BSEE or equivalent experience
  • 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
  • Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
  • Solid grasp of SRAM and memory layout principles.
  • Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
  • Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
  • Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
  • Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
  • Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
  • Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.

Ways to stand out from the crowd:
  • Experience in scripting using Cadence SKILL, Python, or comparable languages for layout automation, checks, reporting, or improving workflows.
  • Strong familiarity with EM/IR, reliability, density, fill, DFM, and post-processing closure at both IP and top level.

Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 132,000 USD - 207,000 USD for Level 4, and 148,000 USD - 235,750 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until June 17, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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About Nvidia

Sourced by ZipRecruiter

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1993

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