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Associate Sram Design Engineer Jobs in Chicago, IL

Lead Design Engineer

Cary, IL · On-site

$104K - $136K/yr

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational ... Detailed knowledge about industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe ...

We are dedicated to the well-being of our associates and are proud to be consistently recognized as ... Provide value engineering reviews and alternate design options in order to maximize cost savings ...

Scholarship for associates' children up to $28,000 per child * 1-month paid sabbatical after every ... Provide value engineering reviews and alternate design options in order to maximize cost savings ...

Scholarship for associates' children up to $28,000 per child * 1-month paid sabbatical after every ... Provide value engineering reviews and alternate design options in order to maximize cost savings ...

The Company is powered by approximately 13,000 dedicated and talented associates. Visit us at www ... In everything the Lead Design Engineer does, both in projects and daily tasks, LEAN Process ...

Summary Electrical Engineer needed to design and develop new products and modify and improve ... Coach and mentor associates assigned to projects * Travel expected (10%) with some international ...

Summary Electrical Engineer needed to design and develop new products and modify and improve ... Coach and mentor associates assigned to projects * Travel expected (10%) with some international ...

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Showing results 1-20

Associate Sram Design Engineer information

See Chicago, IL salary details

$42.8K

$85.1K

$136K

How much do associate sram design engineer jobs pay per year?

As of Aug 3, 2026, the average yearly pay for associate sram design engineer in Chicago, IL is $85,127.00, according to ZipRecruiter salary data. Most workers in this role earn between $67,500.00 and $97,900.00 per year, depending on experience, location, and employer.

What is the difference between Associate Sram Design Engineer vs Memory Design Engineer?

AspectAssociate Sram Design EngineerMemory Design Engineer
CredentialsBachelor's in Electrical Engineering or related field; some roles may prefer a Master'sBachelor's or Master's in Electrical Engineering, Computer Engineering, or related discipline
Work EnvironmentDesign teams in semiconductor or electronics companies, focusing on SRAM architecture and circuit designMemory development teams working on various types of memory, including SRAM, DRAM, and Flash
Industry UsageCommonly used in semiconductor companies, consumer electronics, and hardware startupsWidely used across semiconductor, consumer electronics, and data storage industries

While both roles involve memory technology and circuit design, an Associate Sram Design Engineer specializes specifically in SRAM architecture and design, whereas a Memory Design Engineer may work on a broader range of memory types. The Associate Sram Design Engineer typically focuses on SRAM-related projects within semiconductor companies, making it a more specialized position.

What are Associate SRAM Design Engineers?

Associate SRAM Design Engineers are entry-level professionals who work on the design, development, and verification of Static Random Access Memory (SRAM) circuits, which are crucial components in microprocessors and various digital devices. They assist senior engineers in tasks such as circuit schematic design, layout, simulation, and testing to ensure optimal performance, power efficiency, and reliability of SRAM blocks. Their role often involves working with electronic design automation (EDA) tools and collaborating with cross-functional teams to deliver robust memory solutions. This position is ideal for individuals with a background in electrical or electronics engineering and a strong understanding of digital circuit design principles.

What are the key skills and qualifications needed to thrive as an Associate SRAM Design Engineer, and why are they important?

To thrive as an Associate SRAM Design Engineer, you need a solid background in electrical engineering, CMOS circuit design, and semiconductor device physics, usually supported by a relevant degree. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), scripting languages, and possibly knowledge of Verilog or SPICE simulations is typically required. Strong problem-solving abilities, attention to detail, and effective teamwork are important soft skills in this role. These competencies are crucial to ensure accurate, reliable memory designs that meet performance, power, and area specifications in a collaborative engineering environment.

What are some common challenges an Associate SRAM Design Engineer may face when transitioning from academic projects to industry roles?

In transitioning from academia to an industry role as an Associate SRAM Design Engineer, you may encounter challenges such as adapting to strict project timelines, collaborating closely with cross-functional teams, and adhering to standardized design and verification flows. Unlike academic projects, industry work often requires balancing innovation with strict adherence to design specifications, power/performance constraints, and manufacturability. Additionally, you'll need to quickly become proficient with industry-standard EDA tools, scripting, and revision control systems, as well as participate in regular design reviews and debugging sessions with senior engineers.
What are the most commonly searched types of Sram Design Engineer jobs in Chicago, IL? The most popular types of Sram Design Engineer jobs in Chicago, IL are:
What cities near Chicago, IL are hiring for Associate Sram Design Engineer jobs? Cities near Chicago, IL with the most Associate Sram Design Engineer job openings:
Infographic showing various Associate Sram Design Engineer job openings in Chicago, IL as of July 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $85,127 per year, or $40.9 per hour.

$104K - $136K/yr

Full-time

Posted 11 days ago


Cadence Design Systems rating

9.0

Company rating: 9.0 out of 10

Based on 5 frontline employees who took The Breakroom Quiz

33rd of 241 rated software companies


Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We offer amazing opportunities to grow, no matter where you are in your career.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadenceis a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
  • Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success
  • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
  • You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day.

Job Responsibility

Palladium and Protium are high-capacitive, high-performance hardware assisted verification for complexed System-On-Chip (SOC). This role is to implement, verify, timing closure to tape out Palladium and Protium SOCs.

  • Work on RTL synthesis and floorplanning
  • Build clock trees and perform optimizations
  • Close timing, IR drop and physical verification
  • Review and Document designs for taping out
  • Interface with Front End RTL design teams and Back End Verification teams

Position Requirements/Qualifications:

  • BSdegreeinElectricalEngineeringwithaminimumof5yearsofexperienceORMSwithaminimumof3yearsofexperience
  • Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus
  • Experience with advanced technologies like 5nm, 3ns and 2nm nodes
  • Experience using Linux servers, Script development using Shell/Perl/TCL/Python
  • Detailed knowledge about industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe, etc.
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