Moorestown, NJ · On-site
$128K - $164K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
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Moorestown, NJ · On-site
$128K - $164K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
... FPGA, ASIC, software-based solutions) * Design, model, and validate RF and optical networks ... Strong experience in end to end systems engineering, system performance evaluation, and analysis
... FPGA, ASIC, software-based solutions) * Design, model, and validate RF and optical networks ... Strong experience in end to end systems engineering, system performance evaluation, and analysis
Philadelphia, PA · On-site
$131K - $168K/yr
Overview As an FPGA Engineer at Susquehanna, you will sit at the cusp of hardware and trading and ... What we're looking for * 8+ years of experience in FPGA or ASIC high level architecture, design ...
Philadelphia, PA · On-site
$131K - $168K/yr
Overview As an FPGA Engineer at Susquehanna, you will sit at the cusp of hardware and trading and ... What we're looking for * 8+ years of experience in FPGA or ASIC high level architecture, design ...
Moorestown, NJ · On-site
$128K - $164K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
Moorestown, NJ · On-site
$128K - $164K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
Harrisonville, NJ · On-site
$129K - $166K/yr
... Development Engineer to design and implement FPGA functionality using SystemVerilog for our ... not an ASIC design position. You'll join a highly collaborative, globally distributed R&D ...
Harrisonville, NJ · On-site
$129K - $166K/yr
... Development Engineer to design and implement FPGA functionality using SystemVerilog for our ... not an ASIC design position. You'll join a highly collaborative, globally distributed R&D ...
Camden, NJ · On-site
Establishes design concepts, criteria and engineering efforts for product research, development ... ASIC Engineering development, system and product qualification and NSA certification, low-rate ...
Camden, NJ · On-site
Establishes design concepts, criteria and engineering efforts for product research, development ... ASIC Engineering development, system and product qualification and NSA certification, low-rate ...
Camden, NJ · On-site
$125K - $232K/yr
Establishes design concepts, criteria and engineering efforts for product research, development ... ASIC Engineering development, system and product qualification and NSA certification, low-rate ...
Camden, NJ · On-site
$125K - $232K/yr
Establishes design concepts, criteria and engineering efforts for product research, development ... ASIC Engineering development, system and product qualification and NSA certification, low-rate ...
$94.9K - $104.8K
16% of jobs
$104.8K - $114.7K
3% of jobs
$114.7K - $124.6K
4% of jobs
$127.5K is the 25th percentile. Wages below this are outliers.
$124.6K - $134.5K
6% of jobs
The median wage is $140.7K / yr.
$134.5K - $144.4K
33% of jobs
$144.4K - $154.3K
3% of jobs
$154.3K - $164.2K
2% of jobs
$170.7K is the 75th percentile. Wages above this are outliers.
$164.2K - $174.1K
12% of jobs
$174.1K - $184K
5% of jobs
$184K - $193.9K
4% of jobs
$193.9K - $203.8K
12% of jobs
$94.9K
$151.6K
$203.8K
An ASIC RTL Design Engineer is responsible for designing and implementing the digital logic of Application-Specific Integrated Circuits (ASICs) using Hardware Description Languages (HDLs) like Verilog or VHDL. They translate system-level specifications into Register Transfer Level (RTL) code, ensuring functionality, performance, and power efficiency. Their role also involves simulation, synthesis, timing analysis, and debugging to verify and optimize the design. They collaborate with verification, physical design, and firmware teams to ensure seamless integration.
As an ASIC RTL Design Engineer, your daily responsibilities often include designing and verifying Register Transfer Level (RTL) code for specific chip modules, running simulations, and debugging functional issues. You will frequently collaborate with verification engineers, physical design teams, and system architects to ensure the design meets specifications and performance goals. The role also involves attending regular team meetings to coordinate project tasks and document progress. Staying current with evolving industry methodologies and engaging in code reviews are also part of the typical workflow.
To thrive as an ASIC RTL Design Engineer, you need a strong background in digital logic design, Verilog or VHDL coding, and a relevant degree in electrical or computer engineering. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, and ModelSim, as well as familiarity with simulation and synthesis processes, is typically required. Attention to detail, strong problem-solving abilities, and effective communication skills are highly valued in this position. These competencies are essential to ensuring robust, efficient, and collaborative chip development within project timelines.
The most popular types of Asic Rtl Design Engineer jobs in Philadelphia, PA are:
For Asic Rtl Design Engineer jobs in Philadelphia, PA, the most frequently searched job titles are:
The top searched job categories for Asic Rtl Design Engineer jobs in Philadelphia, PA are:
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RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment, Vivado, GHDL, Questa, Quartus Prime, Zynq, Agilex, AXI, ACE, Avalon, FPGA verification tools, reverse engineering, cocotb, pyuvm
Full Time
Travel required to 10%.
Must be able to apply for and maintain a U.S. Government Security Clearance
FPGA Engineer
The EndoSec FPGA Engineer is responsible for the design, development, testing, and maintenance of IP cores and FPGA-based systems used in hardware security applications.
Key Responsibilities
FPGA Design and Development: Design and develop IP cores and FPGA configurations implementing the latest in leakage-resilient hardware cryptography algorithms using state-of-the-art FPGA hardware.
Modeling and Simulation: Use simulation tools and verification frameworks to ensure mathematically-correct logic before hardware deployment.
Hardware/Software Design: Work closely with other engineers to integrate FPGA designs with application software and embedded systems. Implement embedded software-based testing solutions where applicable to validate FPGA designs.
Performance Optimization: Optimize FPGA designs for timing, resource utilization, and throughput. Identify and resolve system bottlenecks.
Testing and Validation: Create comprehensive test and verification plans for FPGA components, conduct unit and integration testing, and validate hardware performance against requirements in a remote environment.
System Integration: Ensure seamless integration between internally-developed and third-party IP cores, FPGA designs, and embedded systems. Collaborate with other engineers to develop and maintain system-level architecture.
Troubleshooting and Debugging: Utilize debugging tools and techniques to diagnose and resolve issues within FPGA designs and hardware platforms.
Documentation: Prepare detailed documentation, including design specifications, testing protocols, and user guides, to support system development and maintenance.
Continuous Learning: Actively stay up-to-date with the latest advancements in FPGA technology and hardware security to continually refine and enhance system capabilities.
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Guided missile and space vehicle manufacturing
11 - 50 Employees
Washington, DC, US
2013
