DFT Application Engineer
Phoenix, AZ · On-site
Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Self-driven and results-oriented with ability to manage multiple complex tasks effectively
DFT Application Engineer
Phoenix, AZ · On-site
Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Self-driven and results-oriented with ability to manage multiple complex tasks effectively
Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ
Tucson, AZ · On-site
$116K - $160K/yr
Manage moderately sized projects or processes * Viewed as subject-matter expert within discipline ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Principal Electrical Engineer-FPGA Design- Onsite Tucson, AZ
Tucson, AZ · On-site
$116K - $160K/yr
Manage moderately sized projects or processes * Viewed as subject-matter expert within discipline ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Manage moderately sized projects or processes * Viewed as subject-matter expert within discipline ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Manage moderately sized projects or processes * Viewed as subject-matter expert within discipline ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Professional knowledge of ASIC/FPGA Radiation Hardening techniques * Strong technical and project and problem-solving skills. * Experience technically managing people. * Some experience with Analog ...
Professional knowledge of ASIC/FPGA Radiation Hardening techniques * Strong technical and project and problem-solving skills. * Experience technically managing people. * Some experience with Analog ...
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
Design documentation and configuration management are required. What You Will Do * Design and ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques
... ASIC and standard product offerings - Document electrical characteristics, timing diagrams ... Knowledge of IC packaging, thermal management, and power delivery considerations * Proficiency in ...
Quick apply
... ASIC and standard product offerings - Document electrical characteristics, timing diagrams ... Knowledge of IC packaging, thermal management, and power delivery considerations * Proficiency in ...
Senior FPGA Design Engineer
Chandler, AZ · On-site
$101K - $136K/yr
Utilize strong communication skills to effectively work and communicate with team members and engineering management. Qualifications * Strong digital design engineer with FPGA/ASIC SoC design ...
Quick apply
Senior FPGA Design Engineer
Chandler, AZ · On-site
$101K - $136K/yr
Utilize strong communication skills to effectively work and communicate with team members and engineering management. Qualifications * Strong digital design engineer with FPGA/ASIC SoC design ...
Digital RF Systems Architect with Security Clearance
Tempe, AZ · On-site
$149K - $224K/yr
Develop and manage system and subsystem requirements with a focus on digital architectures * Perform requirements decomposition and allocation to ASIC, FPGA hardware/firmware, and software teams
Digital RF Systems Architect with Security Clearance
Tempe, AZ · On-site
$149K - $224K/yr
Develop and manage system and subsystem requirements with a focus on digital architectures * Perform requirements decomposition and allocation to ASIC, FPGA hardware/firmware, and software teams
Digital RF Systems Architect
Tempe, AZ · On-site
$149K - $224K/yr
Develop and manage system and subsystem requirements with a focus on digital architectures * Perform requirements decomposition and allocation to ASIC, FPGA hardware/firmware, and software teams
Digital RF Systems Architect
Tempe, AZ · On-site
$149K - $224K/yr
Develop and manage system and subsystem requirements with a focus on digital architectures * Perform requirements decomposition and allocation to ASIC, FPGA hardware/firmware, and software teams
You will define how firmware manages complex scale-up topologies, ensures raw hardware performance ... Collaborate heavily with ASIC design, logic design (RTL), and verification teams to define hardware ...
New
You will define how firmware manages complex scale-up topologies, ensures raw hardware performance ... Collaborate heavily with ASIC design, logic design (RTL), and verification teams to define hardware ...
New
You will define how firmware manages complex scale-up topologies, ensures raw hardware performance ... Collaborate heavily with ASIC design, logic design (RTL), and verification teams to define hardware ...
New
Quick apply
You will define how firmware manages complex scale-up topologies, ensures raw hardware performance ... Collaborate heavily with ASIC design, logic design (RTL), and verification teams to define hardware ...
New
Digital RF Systems Architect
Tempe, AZ · On-site
$149K - $224K/yr
Develop and manage system and subsystem requirements with a focus on digital architectures * Perform requirements decomposition and allocation to ASIC, FPGA hardware/firmware, and software teams
Digital RF Systems Architect
Tempe, AZ · On-site
$149K - $224K/yr
Develop and manage system and subsystem requirements with a focus on digital architectures * Perform requirements decomposition and allocation to ASIC, FPGA hardware/firmware, and software teams
Senior Ethernet Product Manager
$125K - $165K/yr
Experience with ASIC/SoC development cycles and vendor management. * Experience in contract negotiations and background in supply chain operations for silicon products Why Join Intel Join a team that ...
New
Senior Ethernet Product Manager
$125K - $165K/yr
Experience with ASIC/SoC development cycles and vendor management. * Experience in contract negotiations and background in supply chain operations for silicon products Why Join Intel Join a team that ...
New
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Senior Principal Electrical Engineer-FPGA Design - Onsite Tucson with Security Clearance
Tucson, AZ · On-site
$96K - $130K/yr
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Senior Principal Electrical Engineer-FPGA Design - Onsite Tucson with Security Clearance
Tucson, AZ · On-site
$96K - $130K/yr
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Design documentation and configuration management are required. This position is 100% ONSITE in ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Asic Manager information
What are the key skills and qualifications needed to thrive as an ASIC manager?
To thrive as an ASIC Manager, you need deep expertise in digital and analog integrated circuit design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with EDA tools like Cadence, Synopsys, and Mentor Graphics, as well as knowledge of verification methodologies and relevant industry certifications, is crucial. Strong leadership, problem-solving abilities, and excellent communication skills help in managing cross-functional teams and collaborating with stakeholders. These skills ensure successful delivery of complex ASIC projects, meeting quality, timeline, and budget requirements.
What is an ASIC manager?
An ASIC Manager is a professional responsible for overseeing the design, development, and implementation of Application-Specific Integrated Circuits (ASICs). They coordinate teams of engineers, manage project timelines, and ensure that ASIC projects meet technical and business requirements. ASIC Managers often collaborate with other departments, handle resource allocation, and address technical challenges throughout the development process. Their role is crucial in industries like electronics, telecommunications, and computing, where custom hardware solutions are needed for optimized performance.
What is the difference between Asic Manager vs Asic Engineer?
| Aspect | Asic Manager | Asic Engineer |
|---|---|---|
| Responsibilities | Oversees ASIC design projects, manages teams, coordinates with stakeholders | Designs, develops, and tests ASIC chips |
| Required Skills | Leadership, project management, ASIC design knowledge | Hardware description languages, circuit design, verification |
| Certifications | Typically none required, but PMP or management certifications helpful | ASIC design certifications or relevant technical training |
| Work Environment | Office-based, team management, project coordination | Design labs, engineering teams, hardware development |
The main difference between an Asic Manager and an Asic Engineer lies in their roles. The Asic Manager oversees projects and manages teams, focusing on coordination and leadership. In contrast, the Asic Engineer is hands-on, involved in designing and testing ASIC chips. Both roles require technical ASIC knowledge, but the Manager emphasizes leadership and project oversight, while the Engineer concentrates on technical design work.
What are the most common challenges ASIC managers face when leading design teams, and how can they address them?
ASIC Managers often encounter challenges such as balancing project timelines with technical complexities, coordinating cross-functional teams, and ensuring effective communication between design, verification, and testing groups. Managing evolving project requirements while maintaining quality standards can also be demanding. Success in this role typically relies on proactive project management, clear delegation of tasks, and fostering a collaborative team environment. Leveraging agile methodologies and regular check-ins can help address these challenges and keep projects on track.
What are popular job titles related to Asic Manager jobs in Arizona? For Asic Manager jobs in Arizona, the most frequently searched job titles are:
What job categories do people searching Asic Manager jobs in Arizona look for? The top searched job categories for Asic Manager jobs in Arizona are:
What cities in Arizona are hiring for Asic Manager jobs? Cities in Arizona with the most Asic Manager job openings:
Full-time
Medical, Retirement, PTO
Re-posted 27 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 156 rated electronics manufacturers
Job description
Job Details:
Job Description:
About Intel Foundry Services
Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
Position Overview
We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role supports Aerospace, Defense, and Government (ADG) customers in achieving successful tape-outs while ensuring the highest quality standards through comprehensive DFT solutions and customer engagement.
Key Responsibilities
Customer Technical Support & Collaboration
DFT Methodology & Quality Leadership
Technical Content Development & Training
Essential Skills & Attributes
Qualifications:
The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Preferred Qualifications
What We Offer
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
US, California, Santa Clara, US, Oregon, Hillsboro
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Job Description:
About Intel Foundry Services
Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
Position Overview
We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role supports Aerospace, Defense, and Government (ADG) customers in achieving successful tape-outs while ensuring the highest quality standards through comprehensive DFT solutions and customer engagement.
Key Responsibilities
Customer Technical Support & Collaboration
- Provide comprehensive DFT tool/flow/methodology support to address customer issues and challenges, ensuring successful tape-outs and maximum customer satisfaction
- Work closely with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors to resolve complex technical issues
- Deliver customer-facing technical support and guidance on DFT implementation strategies
DFT Methodology & Quality Leadership
- Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations
- Collaborate with RTL and Hard IP designers on DFT/DFM implementation methodology and work with physical designers on DFT/DFM physical implementation, validation, and timing signoff
- Develop and optimize DFT insertion flows for advanced CMOS processes and multi-die designs
Technical Content Development & Training
- Develop application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
- Create best practice guidelines and methodology documentation for DFT implementation across various design complexities
- Support knowledge transfer and capability building for both internal teams and customer organizations
Essential Skills & Attributes
- Customer-Focused: Strong customer-oriented attitude and mindset with commitment to customer success
- Self-Motivated: Self-driven and results-oriented with ability to manage multiple complex tasks effectively
- Collaborative: Excellent teamwork skills to drive innovative solutions for customer design implementation challenges
- Analytical: Strong analytical problem-solving capabilities for complex DFT challenges
- Communication: Effective communication skills with experience in collaboration, active listening, and providing constructive technical feedback
Qualifications:
The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
- US Citizenship required
- Ability to obtain US Government Security Clearance
- Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field
- 3+ years of experience with advanced CMOS processes (22nm and below)
- 3+ years of combined experience in the following: implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) at both ASIC design block level and full chip level, including ATPG validation and DFT timing/signoff at SOC level
- 2+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting)
Preferred Qualifications
- Active US Government Security Clearance with a minimum of Secret Level.
- Post-graduate degree in Electrical/Computer Engineering or STEM-related field
- Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability
- Proficiency with major EDA tools for MBIST insertion, hierarchical SCAN and JTAG insertion, DFT constraint generation and ATPG validation for single die and multi-die designs
- Experience building/developing quality DFT/DFX insertion flow and ATPG validation flow
- Experience providing technical direction to engineering teams and customer support
- Customer-facing experience in technical roles
- Experience with state-of-the-art process technology (7nm and below) and PDK-based technology evaluation
What We Offer
- Opportunity to work with cutting-edge DFT technologies for aerospace, defense, and government applications
- Direct customer engagement and technical leadership in advanced semiconductor design
- Access to Intel's most advanced foundry technologies and comprehensive EDA tool suites
- Competitive compensation
- Professional development in DFT methodologies and foundry services
- Direct impact on national security through advanced semiconductor technology solutions
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Arizona, Phoenix
Additional Locations:
US, California, Santa Clara, US, Oregon, Hillsboro
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968