Grand Prairie, TX · On-site
$88/hr
ASIC & FPGA Design Engineering - HYBRID LOCATION: (HYBRID) Grand Prairie, TX PAY RATE: $88.99/hour ... and direct hire placements. We deliver expert workforce solutions across engineering, IT, ...
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Grand Prairie, TX · On-site
$88/hr
ASIC & FPGA Design Engineering - HYBRID LOCATION: (HYBRID) Grand Prairie, TX PAY RATE: $88.99/hour ... and direct hire placements. We deliver expert workforce solutions across engineering, IT, ...
Richardson, TX · On-site
$200 - $250/hr
Director, Manufacturing and Test Engineering * Job Title: Director, Manufacturing and Test ... Oversee SMEs focused on high‑power ASIC thermal modeling, liquid Thermal Interface Materials (TIM ...
Richardson, TX · On-site
$200 - $250/hr
Director, Manufacturing and Test Engineering * Job Title: Director, Manufacturing and Test ... Oversee SMEs focused on high‑power ASIC thermal modeling, liquid Thermal Interface Materials (TIM ...
Director, Manufacturing and Test Engineering 2 Functional Area: Engineering (ENG) Career Stream ... Oversee Subject Matter Experts (SMEs) focused on high-power ASIC thermal modeling, liquid Thermal ...
Director, Manufacturing and Test Engineering 2 Functional Area: Engineering (ENG) Career Stream ... Oversee Subject Matter Experts (SMEs) focused on high-power ASIC thermal modeling, liquid Thermal ...
Director, Manufacturing and Test Engineering 2 Functional Area: Engineering (ENG) Career Stream ... Oversee Subject Matter Experts (SMEs) focused on high-power ASIC thermal modeling, liquid Thermal ...
Director, Manufacturing and Test Engineering 2 Functional Area: Engineering (ENG) Career Stream ... Oversee Subject Matter Experts (SMEs) focused on high-power ASIC thermal modeling, liquid Thermal ...
Director, Manufacturing and Test Engineering 2 Functional Area: Engineering (ENG) Career Stream ... Oversee Subject Matter Experts (SMEs) focused on high-power ASIC thermal modeling, liquid Thermal ...
Director, Manufacturing and Test Engineering 2 Functional Area: Engineering (ENG) Career Stream ... Oversee Subject Matter Experts (SMEs) focused on high-power ASIC thermal modeling, liquid Thermal ...
We are expanding our capabilities across Semiconductor, Medical, and Defense markets-advancing technology development, full-custom ASIC/SoC design, and complex electronics programs. Our culture is ...
We are expanding our capabilities across Semiconductor, Medical, and Defense markets-advancing technology development, full-custom ASIC/SoC design, and complex electronics programs. Our culture is ...
Dallas, TX · On-site
$121K - $167K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Dallas, TX · On-site
$121K - $167K/yr
Designs are verified against requirements using both directed test and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Mckinney, TX · On-site
$120K - $155K/yr
Designs are verified against requirements using both directed tests and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Mckinney, TX · On-site
$120K - $155K/yr
Designs are verified against requirements using both directed tests and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
$120K - $155K/yr
Designs are verified against requirements using both directed tests and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
$120K - $155K/yr
Designs are verified against requirements using both directed tests and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Mckinney, TX · On-site
$120K - $155K/yr
Designs are verified against requirements using both directed tests and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Mckinney, TX · On-site
$120K - $155K/yr
Designs are verified against requirements using both directed tests and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Mckinney, TX · On-site
$120K - $155K/yr
Designs are verified against requirements using both directed tests and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Mckinney, TX · On-site
$120K - $155K/yr
Designs are verified against requirements using both directed tests and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Plano, TX · On-site
$130K - $158K/yr
and other details - We are seeking an ASIC Design Verification Engineer whose role will be to ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...
Quick apply
Plano, TX · On-site
$130K - $158K/yr
and other details - We are seeking an ASIC Design Verification Engineer whose role will be to ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...
Mckinney, TX · On-site
$80 - $100/hr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... directed energy, hypersonics, avionics and cybersecurity. The company, formed in 2020 through the ...
New
Mckinney, TX · On-site
$80 - $100/hr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... directed energy, hypersonics, avionics and cybersecurity. The company, formed in 2020 through the ...
New
Mckinney, TX · On-site
$129K - $157K/yr
Verify designs utilizing self-checking techniques with directed and constrained random tests, while ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)
Mckinney, TX · On-site
$129K - $157K/yr
Verify designs utilizing self-checking techniques with directed and constrained random tests, while ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)
Mckinney, TX · On-site
$129K - $157K/yr
Verify designs utilizing self-checking techniques with directed and constrained random tests, while ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)
Mckinney, TX · On-site
$129K - $157K/yr
Verify designs utilizing self-checking techniques with directed and constrained random tests, while ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)
Mckinney, TX · On-site
$129K - $157K/yr
Verify designs utilizing self-checking techniques with directed and constrained random tests, while ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)
Mckinney, TX · On-site
$129K - $157K/yr
Verify designs utilizing self-checking techniques with directed and constrained random tests, while ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)
Mckinney, TX · On-site
$129K - $157K/yr
Verify designs utilizing self-checking techniques with directed and constrained random tests, while ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)
Mckinney, TX · On-site
$129K - $157K/yr
Verify designs utilizing self-checking techniques with directed and constrained random tests, while ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
... directed and constrained random tests, while tracking functional and code coverage * Demonstrate technical expertise in digital signal processing, FPGA/ASIC design/verification, CCA design ...
Support design verification utilizing self-checking techniques with directed and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Support design verification utilizing self-checking techniques with directed and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Support design verification utilizing self-checking techniques with directed and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
Support design verification utilizing self-checking techniques with directed and constrained random ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)
| Aspect | Asic Director | Asic Engineer |
|---|---|---|
| Credentials | Typically requires a Bachelor's or Master's in Electrical Engineering or Computer Engineering; leadership experience | Requires a Bachelor's or Master's in Electrical Engineering or Computer Engineering; technical expertise |
| Work Environment | Leadership roles overseeing teams, project management, strategic planning | Design, develop, and test ASIC chips; hands-on technical work |
| Industry Usage | Used in companies designing complex integrated circuits, often in senior or managerial contexts | Commonly employed in semiconductor companies, focusing on chip design and verification |
The main difference between an Asic Director and an Asic Engineer lies in their responsibilities and experience level. The Asic Director oversees teams and strategic projects, requiring leadership skills and experience, while the Asic Engineer focuses on technical design and development of ASIC chips. Both roles require similar educational backgrounds, but their scope and focus differ significantly.
For Asic Director jobs in Addison, TX, the most frequently searched job titles are:
Cities near Addison, TX with the most Asic Director job openings:
$88/hr
Contractor
Medical, Dental, Vision
Re-posted 19 days ago
JOB TITLE: ASIC & FPGA Design Engineering - HYBRID
LOCATION: (HYBRID) Grand Prairie, TX
PAY RATE: $88.99/hour
We are a national aerospace and defense staffing agency seeking highly qualified candidates for a position with a top-tier client.
Job Details:
Job Type: Contract (12 months with potential for extension)
Clearance: Ability to obtain a Secret Security Clearance.
Industry: Aerospace / Defense / Aviation
Benefits: Medical, dental, and vision (Cigna)
Perks: Bonus potential + Priority access via Tier 1 supplier
Openings Nationwide: Thousands of opportunities across the U.S.
Shift: 4/10A-1st Shift
Qualifying Questions:
Are you a U.S. citizen and able to obtain and maintain a U.S. security clearance?
Do you meet the educational and experience requirements for this role?
Can you commute to the job location or relocate if necessary?
Summary:
Defines architecture and design specifications for ASIC and FPGA components.
Writes clean, maintainable RTL using VHDL, Verilog, and SystemVerilog that meets performance, power, and reliability goals.
Develops synthesis, place and route, and timing closure strategies for deterministic operation on target devices.
Creates comprehensive test plans, simulation models, and verification environments using UVM, SystemC, and Python-based testbenches.
Leads hardware-in-the-loop (HIL) testing, board level debugging, and integration with subsystem hardware.
Conducts timing analysis, power budgeting, and resource utilization studies to optimize device selection and FPGA utilization.
Manages configuration control using GitLab, maintains version-controlled repositories, and ensures full traceability of all artifacts.
Produces complete design documentation including specifications, test plans, verification reports, and release packages that comply with aerospace standards.
Collaborates with systems, software, hardware, mechanical, test, manufacturing, and quality teams for seamless integration and milestone compliance.
Applies knowledge of digital design principles including timing analysis, clock domain crossing, and signal integrity.
Requirements:
Ability to obtain a Secret Security Clearance.
Must be a U.S. Person (as defined by ITAR).
Bachelor of Science degree in Electrical Engineering or closely related STEM field from an accredited university.
Minimum 3 years of professional experience with FPGA design and simulation verification or a related discipline.
Proficiency in HDL programming with VHDL, Verilog, and SystemVerilog.
Experience with Xilinx and AMD toolsets including Vivado, Vitis, and Vitis HLS, and UltraScale design methodology.
Experience with FPGA simulation tools such as Synopsys VCS.
Experience with high-speed interfaces including AXI, Ethernet, TCP/IP, PCIe, and serial protocols.
Practical laboratory debug experience with high-speed oscilloscopes, spectrum analyzers, and signal generators.
Familiarity with Synopsys EDA tools.
Must possess or be able to obtain a DoD Secret clearance.
About Us:
The Structures Company is a premier national aerospace and defense staffing agency specializing in contract, contract-to-hire, and direct hire placements. We deliver expert workforce solutions across engineering, IT, production, maintenance, and support roles.
As trusted partners to leading aerospace and defense OEMs and Tier 1 suppliers, we connect professionals with career opportunities to grow and excel in aviation, aerospace, and defense.
Eligibility Requirements:
Must be a U.S. Person (U.S. citizen, lawful permanent resident, or protected individual under 8 U.S.C. § 1324b(a)(3)) to comply with ITAR regulations.
Keywords: aerospace, aviation, engineering, maintenance, aircraft design, defense
Take your career to new heights—apply today!
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