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Asic Digital Verilog Design Verification Engineer Jobs

Broadcom

Design Verification Engineer

San Jose, CA · On-site

$143K - $230K/yr

The engineer will be responsible for a variety of advanced verification tasks such as: verification ... including System Verilog. * Strong experience in ASIC design verification flows and DV ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM ... Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC ...

Google

ASIC Design Verification Engineer, TPU

Sunnyvale, CA · On-site

$159K - $194K/yr

Experience with SystemVerilog/Verilog. Preferred qualifications: * Master's degree or PhD in ... Plan the verification of complex digital design blocks by fully understanding the design ...

Broadcom

Design Verification Engineer

San Jose, CA · On-site

$143K - $230K/yr

The engineer will be responsible for a variety of advanced verification tasks such as: verification ... including System Verilog. * Strong experience in ASIC design verification flows and DV ...

Broadcom Inc.

ASIC Design Verification Engineer

Irvine, CA · On-site

$91K - $152K/yr

Design, implement, and maintain Verification environments using System Verilog and UVM. * Apply ... Collaborate with design engineers on PCIe and other host interfaces. * Contribute to technical ...

Broadcom, Inc.

Design Verification Engineer

San Jose, CA · On-site

$143K - $230K/yr

The engineer will be responsible for a variety of advanced verification tasks such as: verification ... including System Verilog. * Strong experience in ASIC design verification flows and DV ...

Cisco

SR ASIC Design Verification Engineer

San Jose, CA · On-site

$165K - $241K/yr

Prior experience in System Verilog and UVM. * Experience with ASIC design and verification ... digital worlds. These solutions provide customers with unparalleled security, visibility, and ...

Broadcom, Inc.

Design Verification Engineer

San Jose, CA · On-site

$143K - $230K/yr

The engineer will be responsible for a variety of advanced verification tasks such as: verification ... including System Verilog. * Strong experience in ASIC design verification flows and DV ...

Blue Origin LLC

WI · On-site

$269K - $376K/yr

... digital beamforming, packet processing, and control fabrics.* Drive alignment among design ... Expert-level knowledge of System Verilog, UVM, assertions, and verification signoff methodology.

Advanced Micro Devices

$100K - $122K/yr

Verify digital/analog interfaces using real-number models (RNM) of analog macros, including model ... Verilog-AMS * SystemVerilog RTL design experience in an ASIC environment * Firmware/RTL co ...

Meta

ASIC Engineer, Design Verification

Austin, TX · On-site +1

$146K/yr

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are ... what digital connection makes possible today--beyond the constraints of screens, the limits of ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM ... Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC ...

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Asic Digital Verilog Design Verification Engineer information

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$88K

$156.1K

$207K

How much do asic digital verilog design verification engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for asic digital verilog design verification engineer in the United States is $156,077.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $175,500.00 per year, depending on experience, location, and employer.

What is the difference between Asic Digital Verilog Design Verification Engineer vs Asic Digital Verilog Design Engineer?

AspectAsic Digital Verilog Design Verification EngineerAsic Digital Verilog Design Engineer
Primary FocusVerifying digital Verilog designs to ensure functionality and correctnessDesigning digital Verilog hardware components and modules
Skills RequiredVerification methodologies, testbench development, simulation toolsHardware description, RTL coding, synthesis tools
Work EnvironmentSimulation and verification labs, collaboration with design teamsDesign studios, hardware development teams
Common CertificationsVerification certifications, FPGA/ASIC design coursesVerilog/VHDL certifications, digital design courses

In summary, Asic Digital Verilog Design Verification Engineers focus on testing and validating digital designs to catch errors early, while Asic Digital Verilog Design Engineers are responsible for creating the actual hardware descriptions. Both roles require strong Verilog skills but serve different stages of the ASIC development process.

What are popular job titles related to Asic Digital Verilog Design Verification Engineer jobs?

For Asic Digital Verilog Design Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Asic Digital Verilog Design Verification Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $156,077 per year, or $75 per hour.

Design Verification Engineer

San Jose, CA • On-site

Broadcom
Semiconductor and Electronic Component Manufacturing • 10K+ employees
Learn more about Broadcomexternal

$143K - $230K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 22 days ago

Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

19th of 162 rated electronics manufacturers

Job description

Please Note:

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Job Description:

The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements.

The engineer will be responsible for a variety of advanced verification tasks such as: verification environment development using modern verification techniques (System Verilog and UVM); designing verification components such as UVM agents, and behavioral models; implementing coverage and assertions using System Verilog; and developing random & directed test cases against the specification. This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing coverage results. Candidate must be a highly productive individual contributor with a demonstrated technical capability in system and sub-block level verification.

Job Requirements:

  • A Bachelor's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent

  • 12+ years relevant industry experience preferred

  • Experience in verifying designs at system level and block level.

  • Fluent knowledge of RTL verification methodologies including System Verilog.

  • Strong experience in ASIC design verification flows and DV methodologies

  • Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills.

  • Strong and independent design debugging capability.

  • Strong verbal and written communication skills. Must be comfortable working in a team environment with verification team and design team members.

  • Demonstrated ability to analyze and resolve complex verification trade-off scenarios.

  • Must have legal authorization to work in the US

The candidate should have expertise in some (or preferably all) of the following areas:

  • Experience with hardware design and debug, C++/SystemC and other programming languages are a strong plus.

  • Experience working with Emulators and FPGA based prototyping a plus.

  • Familiarity with overall chip design methodologies and tools

  • Knowledge of CPU, DDR, Bus Protocol, Network Protocol or DSP design preferred

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is$143,800 - $230,000.

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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