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Asic Design Memory Controller Jobs (NOW HIRING)

Design and implement memory controllers : including DDR5/LPDDR5X PHY-side controller logic, HBM3/HBM3E pseudo-channel controllers, command scheduling (open-page/close-page policies, bank-level ...

Description The ideal candidate will have experience in ASIC design with: - Architecture research ... memory subsystem, including dram controller, PHY architecture and design, DFI interface and dram ...

System Performance Modeling Engineer

San Diego, CA · On-site

$106K - $145K/yr

... memory controller, system cache, CPU, GPU, and multimedia is a plus. Qualifications: * Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification ...

Description The ideal candidate will have experience in ASIC design with: - Architecture research ... memory subsystem, including dram controller, PHY architecture and design, DFI interface and dram ...

Description The ideal candidate will have experience in ASIC design with: - Architecture research ... memory subsystem, including dram controller, PHY architecture and design, DFI interface and dram ...

Description The ideal candidate will have experience in ASIC design with: - Architecture research ... memory subsystem, including dram controller, PHY architecture and design, DFI interface and dram ...

... controller with critical HP proprietary intellectual property that separates HP printers from the ... Memory and storage subsystem (DDR, Flash, eMMC, etc.) * Design database management, scripting and ...

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Asic Design Memory Controller information

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$94K

$150.2K

$202K

How much do asic design memory controller jobs pay per year?

As of Sep 14, 2026, the average yearly pay for asic design memory controller in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is an ASIC Design Memory Controller?

An ASIC (Application-Specific Integrated Circuit) Design Memory Controller is a specialized hardware component designed to manage the communication between a processor and memory devices within an integrated circuit. Its main function is to coordinate data transfers, handle memory requests, and ensure data integrity and optimal performance. ASIC memory controllers are tailored for specific applications, such as networking, automotive, or consumer electronics, to meet unique speed, power, and efficiency requirements. They play a critical role in determining the overall system performance and reliability.

What are the key skills and qualifications needed to thrive as an ASIC Design Memory Controller engineer?

To thrive as an ASIC Design Memory Controller Engineer, you need a solid background in digital design, computer architecture, and memory subsystems, typically with a degree in electrical engineering or a related field. Proficiency with hardware description languages (such as Verilog or VHDL), simulation tools (like ModelSim or Synopsys), and experience with ASIC design flows are essential. Strong analytical thinking, problem-solving ability, and effective teamwork set top performers apart in this role. These skills are crucial for delivering reliable, high-performance memory controller designs that meet project specifications and industry standards.

What are some common challenges faced by ASIC Design Memory Controller engineers when integrating memory subsystems into larger chip architectures?

ASIC Design Memory Controller engineers often encounter challenges such as ensuring compatibility between different memory technologies (like DDR, LPDDR, or HBM) and the overall chip architecture. Timing closure, signal integrity, and meeting power/performance trade-offs are critical aspects that require close collaboration with verification, physical design, and firmware teams. Additionally, translating high-level system requirements into efficient RTL implementation while keeping up with evolving memory standards can be demanding. Proactively communicating with cross-functional teams and staying updated on industry trends are key strategies to overcome these challenges.

What is the difference between Asic Design Memory Controller vs FPGA Design Engineer?

AspectAsic Design Memory ControllerFPGA Design Engineer
Primary FocusDesigning memory controllers for ASIC chipsDesigning FPGA-based digital systems and logic
Required SkillsHardware description languages, memory architecture, verificationHDL, FPGA tools, digital design, prototyping
Work EnvironmentASIC development labs, semiconductor companiesElectronics labs, FPGA manufacturing firms
Industry UsageHigh-volume chip production, integrated circuitsPrototyping, custom hardware solutions

While both roles involve digital hardware design, an Asic Design Memory Controller specializes in creating memory interfaces for ASIC chips, focusing on high-performance, low-latency memory systems. An FPGA Design Engineer works on developing flexible, reconfigurable digital systems using FPGA technology. The roles share skills in HDL and digital design but differ in application and environment.

What are popular job titles related to Asic Design Memory Controller jobs?

For Asic Design Memory Controller jobs, the most frequently searched job titles are:

Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

San Diego, CA • On-site

Qualcomm
Technology, Communication and Media • 10K+ employees

Full-time

Re-posted 8 days ago


Key responsibilities

  • Work on architecture, design (RTL coding), and deployment of high-speed memory subsystems into QCT products.

  • Implement and deliver RTL designs, debug designs, and provide debug support during integration.

  • Perform synthesis, timing closure, physical design support, gate-level simulations, and power analysis.


Qualcomm rating

9.1

Company rating: 9.1 out of 10

Based on 12 frontline employees who took The Breakroom Quiz


Job description

Company:
Qualcomm Technologies, Inc.
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
Job Description
Next Generation, High-Speed, Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team is looking for a Senior ASIC Design Engineers for the next generation high speed HBM/LPDDR/DDR memory subsystems.. The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT products.
The candidate will work on architecture, design (RTL coding), and deployment of the next generation, high-speed memory subsystems into QCT products. You will develop or contribute to the development of architecture and design specifications and drive the micro-architecture of portions of the logic design. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible for debugging your designs and also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks. You will make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.
Qualifications
  • Bachelor's or Masters degree in Science, Engineering, or related field.
  • 5+ years ASIC design, RTL coding, front-end digital design experience
  • 3+ years Hardware Architecture experience

Preferred Qualifications
  • 3-10 years of ASIC design (RTL coding) Preferred
  • Exposure to RTL Design Verification flows is a plus
  • 3+ years of direct Hardware Architecture experience
  • Bachelors degree in Electrical or Computer Engineering and at least 5+ years of experience in high speed digital design Master's degree preferred
  • Experience with the following:
  • LPDDR memory and cache controller, NoC based architectures especially the front end interfacing to the CPU, DSP, and multimedia processors
  • Exposure to HBM memory type designs
  • On-chip tightly coupled SRAM & L3 cache controller architecture/design
  • Experience with x86 or ARM CPU/bus architectures
  • Ordering of memory transactions and methods to enforce proper ordering in order to conform to ISA architecture specification

Education Requirements
Required: Bachelor's, Computer Engineering and/or Electrical Engineering
Preferred: Master's, Computer Engineering and/or Electrical Engineering
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
Pay range and Other Compensation & Benefits:
$140,000.00 - $210,000.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.

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About Qualcomm

Sourced by ZipRecruiter

Qualcomm is enabling a world where everyone and everything can be intelligently connected. You interact with products and technologies made possible by Qualcomm every day, including 5G-enabled smartphones that double as pro-level cameras and gaming devices, smarter vehicles and cities, and the technology behind the smart, connected factories that manufactured your latest purchase. Our powerful connectivity solutions keep you connected—even in remote areas. Qualcomm 5G and AI innovations are the power behind the connected intelligent edge. You’ll find our technologies behind and inside the innovations that deliver significant value across multiple industries and to billions of people every day.

Industry

Technology, communication and media

Company size

10,000+ Employees

Headquarters location

San Diego, CA, US

Year founded

1985