Hillsboro, OR ¡ On-site
Overview As the Principal Memory Controller Architect, you will be part of the team creating the next generation Custom Memory Controller, supporting the latest and upcoming DDR technologies to ...
Hillsboro, OR ¡ On-site
Overview As the Principal Memory Controller Architect, you will be part of the team creating the next generation Custom Memory Controller, supporting the latest and upcoming DDR technologies to ...
Architect the memory hierarchy : including multi-level cache controllers, scratchpad memory managers, coherency protocol engines (where applicable), prefetch engines, and bandwidth partitioning/QoS ...
Architect the memory hierarchy : including multi-level cache controllers, scratchpad memory managers, coherency protocol engines (where applicable), prefetch engines, and bandwidth partitioning/QoS ...
Architect the memory hierarchy : including multi-level cache controllers, scratchpad memory managers, coherency protocol engines (where applicable), prefetch engines, and bandwidth partitioning/QoS ...
Architect the memory hierarchy : including multi-level cache controllers, scratchpad memory managers, coherency protocol engines (where applicable), prefetch engines, and bandwidth partitioning/QoS ...
Austin, TX ¡ On-site
Deep understanding of memory subsystems - caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation * Strong communication and interpersonal ...
Austin, TX ¡ On-site
Deep understanding of memory subsystems - caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation * Strong communication and interpersonal ...
Deep understanding of memory subsystems - caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation * Strong communication and interpersonal ...
Deep understanding of memory subsystems - caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation * Strong communication and interpersonal ...
Austin, TX ¡ On-site
... DDR and memory controller architecture, on-chip interconnects, address translation Strong communication and interpersonal skills along with the ability to work in a dynamic, product oriented ...
Austin, TX ¡ On-site
... DDR and memory controller architecture, on-chip interconnects, address translation Strong communication and interpersonal skills along with the ability to work in a dynamic, product oriented ...
Durham, NC ¡ On-site
... DDR and memory controller architecture, on-chip interconnects, address translation Strong communication and interpersonal skills along with the ability to work in a dynamic, product oriented ...
Durham, NC ¡ On-site
... DDR and memory controller architecture, on-chip interconnects, address translation Strong communication and interpersonal skills along with the ability to work in a dynamic, product oriented ...
Durham, NC ¡ On-site
Deep understanding of memory subsystems - caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation * Strong communication and interpersonal ...
Durham, NC ¡ On-site
Deep understanding of memory subsystems - caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation * Strong communication and interpersonal ...
... DDR and memory controller architecture, on-chip interconnects, address translation Strong communication and interpersonal skills along with the ability to work in a dynamic, product oriented ...
... DDR and memory controller architecture, on-chip interconnects, address translation Strong communication and interpersonal skills along with the ability to work in a dynamic, product oriented ...
Deep understanding of memory subsystems - caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation * Strong communication and interpersonal ...
Deep understanding of memory subsystems - caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation * Strong communication and interpersonal ...
Role Summary We are looking for a Principal Design Engineer to lead RTL development and architecture updates for our Memory Controller subsystem, with deep expertise in the ARM CHI-G (Coherent Hub ...
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Role Summary We are looking for a Principal Design Engineer to lead RTL development and architecture updates for our Memory Controller subsystem, with deep expertise in the ARM CHI-G (Coherent Hub ...
Durham, CA ¡ On-site
Deep understanding of memory subsystems - caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation* Strong communication and interpersonal ...
Durham, CA ¡ On-site
Deep understanding of memory subsystems - caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation* Strong communication and interpersonal ...
... memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products ... We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next ...
... memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products ... We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next ...
San Jose, CA ¡ On-site
$159K/yr
This role will lead a team of verification engineers through architecture updates driven by design changes to the memory controller, ensuring full functional coverage and sign-off quality. Key ...
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San Jose, CA ¡ On-site
$159K/yr
This role will lead a team of verification engineers through architecture updates driven by design changes to the memory controller, ensuring full functional coverage and sign-off quality. Key ...
Work closely with SoC architects, memory controller designers, and board/system teams to cooptimize SoC + memory subsystem architecture, including channel topologies, speed grades, rank/stack ...
Work closely with SoC architects, memory controller designers, and board/system teams to cooptimize SoC + memory subsystem architecture, including channel topologies, speed grades, rank/stack ...
Work closely with SoC architects, memory controller designers, and board/system teams to cooptimize SoC + memory subsystem architecture, including channel topologies, speed grades, rank/stack ...
Work closely with SoC architects, memory controller designers, and board/system teams to cooptimize SoC + memory subsystem architecture, including channel topologies, speed grades, rank/stack ...
Work closely with SoC architects, memory controller designers, and board/system teams to co-optimize SoC + memory subsystem architecture, including channel topologies, speed grades, rank/stack ...
Work closely with SoC architects, memory controller designers, and board/system teams to co-optimize SoC + memory subsystem architecture, including channel topologies, speed grades, rank/stack ...
... memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products ... We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next ...
... memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products ... We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next ...
Mountain View, CA ¡ On-site
... memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products ... We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next ...
Mountain View, CA ¡ On-site
... memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products ... We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next ...
Mountain View, CA ¡ On-site
$158K - $218K/yr
Position Summary We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to ... Understanding of memory controller architecture, memory scheduling, prioritization and QoS
Mountain View, CA ¡ On-site
$158K - $218K/yr
Position Summary We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to ... Understanding of memory controller architecture, memory scheduling, prioritization and QoS
$66.83 - $67.68
4% of jobs
$67.68 - $68.53
15% of jobs
$68.96 is the 25th percentile. Wages below this are outliers.
$68.53 - $69.38
12% of jobs
$69.38 - $70.24
16% of jobs
The median wage is $70.47 / hr.
$70.24 - $71.09
12% of jobs
$71.09 - $71.94
16% of jobs
$71.99 is the 75th percentile. Wages above this are outliers.
$71.94 - $72.79
9% of jobs
$72.79 - $73.65
5% of jobs
$73.65 - $74.50
3% of jobs
$74.50 - $75.35
5% of jobs
$75.35 - $76.20
3% of jobs
$66
$70
$76
| Aspect | Memory Controller Architect | Memory Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience in hardware architecture | Bachelor's or Master's in Electrical Engineering or Computer Engineering; focus on circuit design |
| Work Environment | Design teams, hardware development labs, system architecture planning | Design labs, circuit simulation, chip fabrication facilities |
| Industry Usage | Semiconductor companies, hardware manufacturers, system integrators | Semiconductor companies, hardware manufacturers, integrated circuit design firms |
| Common Search/Comparison | Memory Controller Architect | Memory Design Engineer |
The Memory Controller Architect focuses on designing the overall architecture of memory controllers, ensuring compatibility and performance within systems. In contrast, the Memory Design Engineer concentrates on creating the detailed circuitry of memory modules. Both roles require strong electrical engineering backgrounds and often collaborate during product development, but their focus areas differ from system architecture to circuit design.
For Memory Controller Architect jobs, the most frequently searched job titles are:
Hillsboro, OR ⢠On-site
Full-time
Posted 11 days ago
8.6
Based on 134 frontline employees who took The Breakroom Quiz
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Our infrastructure is comprised of a large global portfolio of more than 100 datacenters and 1 million servers. Our foundation is built upon and managed by a team of subject matter experts working to support services for more than 1 billion customers and 20 million businesses in over 90 countries worldwide. With environmental sustainability and optimization at the forefront of our datacenter design and operations, we continue to grow and evolve as we meet the ever-changing business demands that hold Microsoft as a world-class cloud provider.
Computer and computer peripheral equipment and software wholesalers
10,000+ Employees
Redmond, WA, US
1975
