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Asic Design Engineer Jobs in Raleigh, NC (NOW HIRING)

Nvidia

Senior ASIC Timing Engineer

Durham, NC · On-site

NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices ...

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All JobsAsic Design Engineer JobsAsic Design Engineer Jobs in Raleigh, NC

Asic Design Engineer information

See Raleigh, NC salary details

$91.4K

$146K

$196.3K

How much do asic design engineer jobs pay per year?

As of Jun 12, 2026, the average yearly pay for asic design engineer in Raleigh, NC is $145,994.00, according to ZipRecruiter salary data. Most workers in this role earn between $127,800.00 and $175,000.00 per year, depending on experience, location, and employer.

What is the difference between Asic Design Engineer vs FPGA Design Engineer?

AspectAsic Design EngineerFPGA Design Engineer
CredentialsBachelor's/Master's in Electrical Engineering or Computer EngineeringBachelor's/Master's in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning custom chips for manufacturingDeveloping programmable logic designs for prototyping and deployment
Industry UsageSemiconductor companies, consumer electronics, automotivePrototyping, testing, and specialized hardware applications

Both roles require similar educational backgrounds and often overlap in skills like HDL programming. However, Asic Design Engineers focus on creating chips for mass production, while FPGA Design Engineers work on flexible, reprogrammable hardware for testing and specific applications.

What are some common challenges faced by ASIC Design Engineers during the design and verification phases?

ASIC Design Engineers often encounter challenges such as meeting strict performance and power constraints while ensuring that the design remains within budget and time limits. Debugging complex logic errors during simulation and verification can be particularly demanding, as small mistakes can have significant downstream effects. Additionally, effective communication with cross-functional teams—including software, hardware, and validation engineers—is essential to resolve integration issues and meet project milestones. Adapting to rapidly evolving tools and technologies is also a key part of the role.

Are ASIC design engineers in demand?

ASIC design engineers are in high demand due to the growth of semiconductor, consumer electronics, and telecommunications industries. Their expertise in hardware description languages like VHDL and Verilog, along with experience in FPGA and ASIC development, makes them valuable in developing custom integrated circuits for various applications.

How much do ASIC engineers get paid?

ASIC design engineers typically earn between $80,000 and $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills or certifications can earn higher salaries, often exceeding $180,000. Compensation may also include bonuses and stock options in some organizations.

What are the key skills and qualifications needed to thrive as an ASIC Design Engineer, and why are they important?

To thrive as an ASIC Design Engineer, you need a solid background in electrical engineering, digital logic design, and proficiency with hardware description languages like Verilog or VHDL, usually backed by a relevant degree. Familiarity with EDA tools such as Synopsys or Cadence and knowledge of simulation and verification methodologies are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork set outstanding engineers apart in this role. These skills and qualities are vital for delivering complex, high-performance integrated circuits that meet strict specifications and project deadlines.

What are ASIC Design Engineers?

ASIC Design Engineers are professionals who design and develop Application-Specific Integrated Circuits (ASICs), which are custom-built semiconductor chips tailored for specific applications or products. They are responsible for the entire design process, including architecture definition, logic design, verification, synthesis, and sometimes physical layout. Their work is crucial in industries like consumer electronics, telecommunications, automotive, and more, ensuring that devices have optimized performance, power efficiency, and functionality for their intended uses.

What engineers make $500,000?

Senior engineers in high-demand fields such as software engineering, data science, and specialized roles like ASIC design engineers can earn $500,000 or more annually, especially with experience, advanced skills, and in competitive industries. Executive or leadership positions in engineering firms may also reach this compensation level. Factors like location, company size, and certifications influence salary potential.

What Does an ASIC Design Engineer Do?

An application specific integrated circuit (ASIC) is an electronic circuit created for a specific purpose, rather than for general use. ASIC design engineers create product design specification (PDS) statements for ASIC, optimize logic design, and create architectural design models. ASIC design engineers often work on a team to deliver ASIC design solutions for standard and complex computing. Knowledge of computer-aided design (CAD) tools, logic simulation, Verilog, and other hardware description languages (HDLs) is integral to career success.

What is the salary of ASIC design engineer?

The salary of an ASIC design engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages and verification tools tend to earn higher salaries.
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Asic Design Engineer jobs near you
Infographic showing various Asic Design Engineer job openings in Raleigh, NC as of June 2026, with employment types broken down into 100% Full Time. Highlights an 66% In-person, 17% Hybrid, and 17% Remote job distribution, with an average salary of $145,994 per year, or $70.2 per hour.
Principal Engineer - Design For Test (DFT)

Principal Engineer - Design For Test (DFT)

Marvell

Morrisville, NC

Full-time

Life, Retirement

Posted 18 days ago

Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As a Digital IC Design Principal Engineer with Marvell, you'll be a member of the Custom Silicon Engineering team. This team is a leader in large multi-die designs that drive high compute performance and acceleration in many markets, including custom AI, 5G and 6G. The role will be challenging and will require an experienced DFT engineer that can work with existing DFT solutions while also creating new solutions to address industry first issues.

What You Can Expect

The position will be responsible for implementing DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs. The work will involve running Tessent tools for insertion of all DFT structures. The role will involve chiplet DFT solutions, will include Tessent SSN, and will require strong verification and debug skills.

  • The engineer will need to show proficiency in ICL/PDL, PTAP/STAP, 1687. It is a requirement that the engineer is knowledgeable in instrument-level access inside a chip.
  • The engineer will work with other leads to help with Design-for-Test architecture definition and implementation of additional DFT/DFX features
  • The engineer will also be involved in STA constraint definition, pattern generation & post-silicon bring-up and debug.
  • In this position, the responsibility will grow to include mentoring, guiding and driving a small team of DFT engineers.
  • The engineer will work with other leads to help enhance DFT methodologies and tools.

What We're Looking For

  • Bachelor's, Master's degree or PhD in Computer Science, Electrical Engineering or related fields with minimum of 10 years of work experience.
  • Direct DFT experience with at least 8 years in the custom chip (ASIC) design business
  • Hands-on working experience in various stages of DFT-Execution: SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bring-up/Debug
  • Thorough knowledge on various DFT/Test architecture solutions for 2.5D/3D IC design.
  • Strong fundamentals in digital circuit design and logic design
  • Understanding of DFT flows and methodologies and experience with Siemens/Synopsys Tool set (Tessent, Spyglass/Tmax, Genus, Modus, NCSim/DC), with Tessent the EDA tool flow in use.
  • Proven track record of problem solving and innovation to meet challenging design requirements.
  • Excellent team player and can work with different function leaders, across different geographies to define and execute the DFT project to completion.
  • Excellent communications skills both verbal and written.
  • Scripting skills using Python, PERL, Tcl and C-Shell is plus.

Expected Base Pay Range (USD)

160,400 - 237,320, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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