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Asic Design Engineer Jobs in Raleigh, NC (NOW HIRING)

Nvidia

Senior ASIC Timing Engineer

Durham, NC · Hybrid

We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... Experience in physical design and optimization e.g., synthesis, placement, routing, logic ...

Nvidia

Principal CPU Software Architect

Durham, NC · On-site

... software, ASIC design, verification, and platform teams. Our software architects excel at pushing the state of the art, while making the best engineering trade-offs. What you'll be doing:

Nvidia

EDA Workflow Optimization Engineer

Durham, NC · Hybrid

$107K - $127K/yr

Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow environments. * Hands-on experience with EDA tools. * Experienced in UNIX Systems programming and automation using Python and/or ...

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All JobsAsic Design Engineer JobsAsic Design Engineer Jobs in Raleigh, NC

Asic Design Engineer information

See Raleigh, NC salary details

$91.4K

$146K

$196.3K

How much do asic design engineer jobs pay per year?

As of Jul 4, 2026, the average yearly pay for asic design engineer in Raleigh, NC is $145,994.00, according to ZipRecruiter salary data. Most workers in this role earn between $127,800.00 and $175,000.00 per year, depending on experience, location, and employer.

What is the difference between Asic Design Engineer vs FPGA Design Engineer?

AspectAsic Design EngineerFPGA Design Engineer
CredentialsBachelor's/Master's in Electrical Engineering or Computer EngineeringBachelor's/Master's in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning custom chips for manufacturingDeveloping programmable logic designs for prototyping and deployment
Industry UsageSemiconductor companies, consumer electronics, automotivePrototyping, testing, and specialized hardware applications

Both roles require similar educational backgrounds and often overlap in skills like HDL programming. However, Asic Design Engineers focus on creating chips for mass production, while FPGA Design Engineers work on flexible, reprogrammable hardware for testing and specific applications.

How much does an ASIC design engineer make?

The average salary for an ASIC design engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages and verification tools can earn higher salaries, often exceeding $180,000. Compensation may also include bonuses and stock options in some organizations.

What are some common challenges faced by ASIC Design Engineers during the design and verification phases?

ASIC Design Engineers often encounter challenges such as meeting strict performance and power constraints while ensuring that the design remains within budget and time limits. Debugging complex logic errors during simulation and verification can be particularly demanding, as small mistakes can have significant downstream effects. Additionally, effective communication with cross-functional teams—including software, hardware, and validation engineers—is essential to resolve integration issues and meet project milestones. Adapting to rapidly evolving tools and technologies is also a key part of the role.

Are ASIC design engineers in demand?

ASIC design engineers are in high demand due to the growth of semiconductor technology, consumer electronics, and data centers. They require skills in hardware description languages like VHDL or Verilog and familiarity with EDA tools, making their expertise valuable in industries focused on custom chip development.

What engineer makes $500,000 a year?

An experienced senior ASIC design engineer or hardware engineer working in high-paying industries such as semiconductor or technology companies can earn $500,000 or more annually, especially with bonuses and stock options. These roles typically require advanced skills in digital design, verification, and familiarity with tools like VHDL or Verilog, along with extensive industry experience. Compensation varies based on location, company size, and individual expertise.

What are the key skills and qualifications needed to thrive as an ASIC Design Engineer, and why are they important?

To thrive as an ASIC Design Engineer, you need a solid background in electrical engineering, digital logic design, and proficiency with hardware description languages like Verilog or VHDL, usually backed by a relevant degree. Familiarity with EDA tools such as Synopsys or Cadence and knowledge of simulation and verification methodologies are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork set outstanding engineers apart in this role. These skills and qualities are vital for delivering complex, high-performance integrated circuits that meet strict specifications and project deadlines.

What are ASIC Design Engineers?

ASIC Design Engineers are professionals who design and develop Application-Specific Integrated Circuits (ASICs), which are custom-built semiconductor chips tailored for specific applications or products. They are responsible for the entire design process, including architecture definition, logic design, verification, synthesis, and sometimes physical layout. Their work is crucial in industries like consumer electronics, telecommunications, automotive, and more, ensuring that devices have optimized performance, power efficiency, and functionality for their intended uses.

What Does an ASIC Design Engineer Do?

An application specific integrated circuit (ASIC) is an electronic circuit created for a specific purpose, rather than for general use. ASIC design engineers create product design specification (PDS) statements for ASIC, optimize logic design, and create architectural design models. ASIC design engineers often work on a team to deliver ASIC design solutions for standard and complex computing. Knowledge of computer-aided design (CAD) tools, logic simulation, Verilog, and other hardware description languages (HDLs) is integral to career success.

What is the salary of ASIC design engineer?

The salary of an ASIC design engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages and verification tools tend to earn higher salaries.
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Asic Design Engineer jobs near you
Senior Engineer, Physical Design

Senior Engineer, Physical Design

Marvell

Morrisville, NC • On-site

Full-time

Medical, Retirement, PTO

Posted yesterday

Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Built on decades of expertise and execution, Marvell's custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications.

What You Can Expect

You will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. Every day, you'll be working hands-on to triage workflows, whether you're running RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip, analyzing performance by running timing analysis, verifying a robust power grid by performing EMIR analysis, etc. There are many sign-off checks that need to happen to verify that the database is ready to move on to the next level, and it's your responsibility to review completed runs for errors or create optimizations from successful runs.

We are hiring for multiple office locations. This is a full-time, on-site role, and employees are expected to work at their designated team location. Relocation assistance is available for qualified candidates.

What We're Looking For

  • Bachelor's degree in Computer Science, Electrical Engineering or related fields, or the equivalent work experience that provides knowledge and exposure to theories, principles and concepts

  • Experience in physical design with a focus on block-level PNR for advanced CMOS process nodes (e.g., 7nm, 5nm, or below)

  • Working experience with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, and Synopsys Design Compier, IC Compiler and Fusion Compiler

  • Working knowledge of static timing analysis tools such as Tempus or PrimeTime and EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail is advantageous

  • Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality) is advantageous

  • Enjoy learning by doing the work and having access to guides and a mentor

  • Be willing to raise your hand and volunteer for learning opportunities you may not have experienced before

    Expected Base Pay Range (USD)

    90,400 - 133,760, $ per annum

    The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

    Additional Compensation and Benefit Elements

    At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

    All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

    Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

    Interview Integrity

    As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
    Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

    This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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