About the Role As a Senior Physical Design Engineer, you will play a key role in the implementation ... Strong problem-solving and debug skills across backend implementation challenges * Clear ...
About the Role As a Senior Physical Design Engineer, you will play a key role in the implementation ... Strong problem-solving and debug skills across backend implementation challenges * Clear ...
Physical Design Engineer
Bodega Bay, CA · On-site
$180K - $230K/yr
We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...
Quick apply
Physical Design Engineer
Bodega Bay, CA · On-site
$180K - $230K/yr
We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...
Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)
North Reading, MA · On-site
$192K - $307K/yr
You will guide physical design architecture, mentor engineers, and play a critical role in ... Collaborate with a backend physical design house to support P&R execution, debug flow or ...
Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)
North Reading, MA · On-site
$192K - $307K/yr
You will guide physical design architecture, mentor engineers, and play a critical role in ... Collaborate with a backend physical design house to support P&R execution, debug flow or ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
Physical Design Engineer
Bodega Bay, CA · On-site
$161K - $166K/yr
We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...
Physical Design Engineer
Bodega Bay, CA · On-site
$161K - $166K/yr
We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...
Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)
Reading, MA · On-site
$192K - $307K/yr
You will guide physical design architecture, mentor engineers, and play a critical role in ... Collaborate with a backend physical design house to support P&R execution, debug flow or ...
Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)
Reading, MA · On-site
$192K - $307K/yr
You will guide physical design architecture, mentor engineers, and play a critical role in ... Collaborate with a backend physical design house to support P&R execution, debug flow or ...
Physical Design Engineer
Milpitas, CA · On-site
$155K - $159K/yr
We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...
Physical Design Engineer
Milpitas, CA · On-site
$155K - $159K/yr
We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...
ASIC/SOC CAD Engineer
Mountain View, CA · On-site
$175K - $400K/yr
MatX is seeking a Physical Design CAD Engineer to join our team as we create best-in-class silicon ... Automate back-end runs, create reports, post-process logs, generate metrics, and extract insights
ASIC/SOC CAD Engineer
Mountain View, CA · On-site
$175K - $400K/yr
MatX is seeking a Physical Design CAD Engineer to join our team as we create best-in-class silicon ... Automate back-end runs, create reports, post-process logs, generate metrics, and extract insights
ASIC Physical Design
$159K - $164K/yr
Here is an ASIC Physical Design role MUST be onsite in the Bay Area though if you can find ... Physical Design engineer to own the entire block Floorplanning, PlacenRoute, Timing Closure DRC/LVS ...
New
Quick apply
ASIC Physical Design
$159K - $164K/yr
Here is an ASIC Physical Design role MUST be onsite in the Bay Area though if you can find ... Physical Design engineer to own the entire block Floorplanning, PlacenRoute, Timing Closure DRC/LVS ...
New
Physical Design Engineer
Austin, TX · On-site
$2.0K/mo
Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD ... Experience with back-end design and timing closure on advanced process nodes (5nm and below)
Physical Design Engineer
Austin, TX · On-site
$2.0K/mo
Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD ... Experience with back-end design and timing closure on advanced process nodes (5nm and below)
ASIC Physical Design
San Jose, CA · On-site
$159K - $164K/yr
Here is an ASIC Physical Design role MUST be onsite in the Bay Area though if you can find ... Physical Design engineer to own the entire block Floorplanning, PlacenRoute, Timing Closure DRC/LVS ...
New
ASIC Physical Design
San Jose, CA · On-site
$159K - $164K/yr
Here is an ASIC Physical Design role MUST be onsite in the Bay Area though if you can find ... Physical Design engineer to own the entire block Floorplanning, PlacenRoute, Timing Closure DRC/LVS ...
New
Physical Design Engineer
San Jose, CA · On-site
$200K - $300K/yr
Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD ... Experience with back-end design and timing closure on advanced process nodes (5nm and below)
Quick apply
Physical Design Engineer
San Jose, CA · On-site
$200K - $300K/yr
Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD ... Experience with back-end design and timing closure on advanced process nodes (5nm and below)
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At ...
Physical Design Engineer
San Jose, CA · On-site
$200K - $300K/yr
Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD ... Experience with back-end design and timing closure on advanced process nodes (5nm and below)
Physical Design Engineer
San Jose, CA · On-site
$200K - $300K/yr
Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD ... Experience with back-end design and timing closure on advanced process nodes (5nm and below)
Physical Design Engineer
San Jose, CA · On-site
$2.0K/mo
Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD ... Experience with back-end design and timing closure on advanced process nodes (5nm and below)
Physical Design Engineer
San Jose, CA · On-site
$2.0K/mo
Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD ... Experience with back-end design and timing closure on advanced process nodes (5nm and below)
Physical Design Engineer
Austin, TX · On-site
$134K - $138K/yr
Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD ... Experience with back-end design and timing closure on advanced process nodes (5nm and below)
Physical Design Engineer
Austin, TX · On-site
$134K - $138K/yr
Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD ... Experience with back-end design and timing closure on advanced process nodes (5nm and below)
Principal ASIC Physical Design Engineer
Seattle, WA · On-site
$190K - $280K/yr
The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design ...
Principal ASIC Physical Design Engineer
Seattle, WA · On-site
$190K - $280K/yr
The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design ...
ASIC Physical Design Engineer
Austin, TX · On-site
$134K - $138K/yr
Job Title: ASIC Physical Design Engineer Location: Austin, TX and Portland, OR Duration: 12+Months Jobs Description: Engineer should have good knowledge on Floor plan, STA and PV flow. Intel ...
ASIC Physical Design Engineer
Austin, TX · On-site
$134K - $138K/yr
Job Title: ASIC Physical Design Engineer Location: Austin, TX and Portland, OR Duration: 12+Months Jobs Description: Engineer should have good knowledge on Floor plan, STA and PV flow. Intel ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Palo Alto, CA · On-site
$175K - $280K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Palo Alto, CA · On-site
$175K - $280K/yr
Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At ...
$175K - $280K/yr
Today the company is actively developing the technologies to make this possible, with the ultimate goal ofenabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At ...
$175K - $280K/yr
Today the company is actively developing the technologies to make this possible, with the ultimate goal ofenabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At ...
Asic Backend Physical Design Engineer information
See salary details
$60.5K - $73.1K
4% of jobs
$73.1K - $85.7K
2% of jobs
$85.7K - $98.3K
2% of jobs
$98.3K - $110.9K
7% of jobs
$110.9K - $123.5K
9% of jobs
$124.7K is the 25th percentile. Wages below this are outliers.
$123.5K - $136K
11% of jobs
$136K - $148.6K
14% of jobs
The median wage is $149.5K / yr.
$148.6K - $161.2K
15% of jobs
$169.1K is the 75th percentile. Wages above this are outliers.
$161.2K - $173.8K
17% of jobs
$173.8K - $186.4K
13% of jobs
$186.4K - $199K
5% of jobs
$60.5K
$147.7K
$199K
How much do asic backend physical design engineer jobs pay per year?
What are popular job titles related to Asic Backend Physical Design Engineer jobs?
For Asic Backend Physical Design Engineer jobs, the most frequently searched job titles are:

Senior Engineer, Physical Design Engineering (ASIC)
Wilmington, MA • On-site
Full-time
Medical, Dental, Vision, Retirement, PTO
Re-posted 14 days ago
Key responsibilities
Own physical design implementation for complex digital blocks and subsystems, including floorplanning, placement, clock tree synthesis, routing, and physical optimization
Drive timing closure, congestion analysis, power optimization, and area improvement across assigned blocks or subsystems
Perform physical verification activities including DRC, LVS, ERC, and reliability checks in collaboration with relevant teams
Analog Devices rating
8.7
Based on 19 frontline employees who took The Breakroom Quiz
Job description
About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.comand on LinkedIn and X.
About the Role
As a Senior Physical Design Engineer, you will play a key role in the implementation and delivery of complex digital and mixed-signal IC designs. You will work across the physical design flow, from floorplanning through place-and-route, timing closure, physical verification, and tapeout support, helping turn architectural and RTL intent into robust silicon implementation. This role requires strong technical depth in physical design, the ability to solve complex implementation challenges, and effective collaboration with cross-functional teams across the development cycle.
Key Responsibilities
- Own physical design implementation for complex digital blocks and subsystems, including floorplanning, placement, clock tree synthesis, routing, and physical optimization
- Drive timing closure, congestion analysis, power optimization, and area improvement across assigned blocks or subsystems
- Perform physical verification activities including DRC, LVS, ERC, and reliability checks in collaboration with relevant teams
- Develop and refine physical design constraints, scripts, and flow improvements to improve quality and execution efficiency
- Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve design and implementation issues
- Support block-level and top-level integration activities, including interface planning, timing constraint alignment, and implementation readiness
- Analyze and debug timing, signal integrity, power, and physical implementation issues across the full backend flow
- Contribute to methodology improvements and help establish best practices for physical design execution
- Participate in design reviews and provide clear technical input on implementation trade-offs, risks, and readiness
- Author and maintain documentation for design implementation, constraints, flows, and signoff status
- Mentor junior engineers on physical design practices, tool usage, and debugging approaches
- Support tapeout planning and execution activities to ensure high-quality delivery against project milestones
Must Have Skills
- Strong experience in physical design for ASIC/SoC development, including successful implementation through tapeout
- Expertise in floorplanning, place-and-route, clock tree synthesis, timing closure, and physical verification
- Strong understanding of timing analysis, constraints, signal integrity, power optimization, and physical design trade-offs
- Experience with industry-standard physical design and signoff tools, including Cadence-based flows
- Scripting experience in TCL, Python, or similar languages for automation and flow improvement
- Experience collaborating across cross-functional teams including RTL, STA, DFT, design verification, and package or product engineering
- Strong problem-solving and debug skills across backend implementation challenges
- Clear communication and technical documentation skills
- Demonstrated ability to independently drive complex blocks or major implementation workstreams
Preferred Qualifications
- Experience with advanced-node implementation and low-power design methodologies
- Familiarity with mixed-signal integration considerations and top-level implementation challenges
- Experience improving backend flows, automation, or methodology
- Prior mentoring experience or informal technical leadership on project execution
Preferred Education and Experience
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field, or an equivalent combination of education and 5+ years of related experience
- Master's degree in Electrical Engineering, Computer Engineering, or related field, or an equivalent combination of education and 5+ years of related experience
We recognize that candidates may not meet every listed requirement. If you bring relevant experience and a willingness to learn, we encourage you to apply.
#LI-PG1
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $116,960 to $160,820.Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.
This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.
This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.
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About Analog Devices
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Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect.
Industry
Electrical equipment, appliance, and component manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Norwood, MA, US