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Arm Design Verification Engineer Jobs (NOW HIRING)

Design Verification Engineer

Sunnyvale, CA ยท On-site

$159K - $194K/yr

Description We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive ...

Design Verification Engineer

Sunnyvale, CA ยท On-site

$159K - $194K/yr

Description We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive ...

Design Verification Engineer

Santa Clara, CA ยท On-site

$159K - $195K/yr

We are seeking a skilled Design Verification Engineer to join our hardware engineering team. The ideal candidate will be responsible for verifying complex digital designs using advanced verification ...

Security IP Verification Engineer

Austin, TX ยท On-site

$161K - $218K/yr

Our Arm Security IP Team is seeking creative and enthusiastic Design Verification Engineers to join our team. We have exciting opportunities in our team for verification engineers with demonstrated ...

Security IP Verification Engineer

Austin, TX ยท Hybrid

$161K - $218K/yr

Our Arm Security IP Team is seeking creative and enthusiastic Design Verification Engineers to join our team. We have exciting opportunities in our team for verification engineers with demonstrated ...

Design Verification Engineer

Dallas, TX ยท On-site

$123K - $151K/yr

As a Design Verification Engineer, you will work across the full verification cycle - from understanding the system/design intent, developing detailed verification plans and building test benches ...

C - Focused Design Verification Engineer

San Diego, CA ยท On-site

$144K - $176K/yr

Description As a C- Focused Design Verification Engineer, you will be at the center of a chip ... Understanding of ARM V7 or V8 architecture is plus Experience in setting UVM/System TB with ...

Design Verification Engineer

San Jose, CA ยท On-site

$159K - $194K/yr

About the role SambaNova Systems is looking for a talented and motivated Design Verification Engineer, DFT to help us build state of the art RDU chips for machine learning and artificial intelligence.

Design Verification Engineer

Palo Alto, CA ยท On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Design Verification Engineer

Knoxville, TN ยท On-site

$129K - $158K/yr

As a Design Verification Engineer, you will work across the full verification cycle - from developing detailed verification plans and building test benches through running coverage regressions ...

Design Verification Engineer

Dallas, TX ยท On-site

$123K - $151K/yr

As a Design Verification Engineer, you will work across the full verification cycle - from understanding the system/design intent, developing detailed verification plans and building test benches ...

Design Verification Engineer

San Jose, CA ยท On-site

$159K - $194K/yr

Design Verification Engineer Location: San Jose, CA - Onsite Contract: 6+ Months with Possible Extension Experience: 8+ years Mandatory Skills: HBM2E/HBM3/HBM3E hands-on verification; SV/UVM; memory ...

New

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Design Verification Engineer

Austin, TX ยท On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Design Verification Engineer

Austin, TX ยท On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Design Verification Engineer

Boise, ID ยท On-site

$129K - $158K/yr

Job Summary As a Design Verification Engineer at Micron Technology, Inc., you'll play a central role in validating complex memory architectures, ensuring speed, reliability, and innovation come ...

Showing results 41-60

Arm Design Verification Engineer information

See salary details

$105.5K

$149.2K

$167K

How much do arm design verification engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for arm design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Arm Design Verification Engineer jobs?

For Arm Design Verification Engineer jobs, the most frequently searched job titles are:

Design Verification Engineer

Sunnyvale, CA โ€ข On-site

$159K - $194K/yr

Full-time

Re-posted yesterday


Job description

Do you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them? Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities and impact on AI industry?
We're looking forward to you joining us to collaborate, contribute, and revolutionize AI silicon and system.
Description
We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive in this highly technical environment. Your job responsibilities as a Design Verification Engineer will help the team to verify the functionality of Baidu's AI SoC at both block level and SoC level.
You will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development.
Run RTL and gate level functional verification, debug failures, lead bug tracking, and analyze and close coverage.
Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model.
Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases, reference model, coverage model and automation of regression suite.
Support emulation and silicon bring up debug with your smart ideas to duplicate the problem in simulation.
Qualifications
  • Minimum 5 years of experience of UVM based verification on a significantly complex project.
  • Advanced knowledge of standard ASIC design and verification flows, simulation and testbench development.
  • Advanced knowledge of System Verilog and the UVM methodology.
  • Solid verification skills in problem solving, constrained random testing, coverage closure, gate level simulations, X propagation.
  • Good practice of one scripting language (Perl, Python, Tcl) no preference.
  • SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache).
  • Familiar with C/C++.
  • Formal Verification (Model Checking, Equivalence Checking).
  • Excellent communication skills in both English and Chinese.

Culture Fit:
  • Mission alignment: If you want to be part of a team to accomplish this great mission, we will provide you the best possible platform to do that.
  • Self-directed: We work best with people that are driven, motivated, and aspire to greatness.
  • Hungry to learn: We are eager to see you learn new skills and grow.
  • Team orientation: We work in small, fast-moving teams. We watch out for each other and go after big goals together as a team.

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