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Apd Jobs in California (NOW HIRING)

Broadcom

ASIC DFT Engineer

San Jose, CA

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourSan Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs ...

Broadcom

ASIC DFT Engineer

San Jose, CA

$141K - $226K/yr

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at ourSan Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs ...

Leidos

Senior Optical Engineer

San Diego, CA · On-site

$110K - $152K/yr

Integrate and characterize highly sensitive detector technologies, including Avalanche Photodiodes (APD), Geiger-mode APDs (GmAPD), and Single Photon Counting Detectors (SPCDs) as well as IR and ...

The Rockridge Group

PCB DESIGN ENGINEER

San Jose, CA · On-site

Experience using Cadence Design Entry HDL or other similar schematics tools (APD, Mentor tools like DX Designer, Expedition) a plus DAY TO DAY: * Create netlist and routing rules (logical Design ...

Apple

Package Integration Engineer

San Francisco, CA · On-site

$122K - $164K/yr

AutoCAD, APD and multi-physics simulation knowledge is a plus. Some hands-on knowledge in Wafer Bumping, Manufacturing assembly processes; such as wafer back-grind, wafer dicing, Flip Chip die attach ...

Broadcom, Inc.

ASIC DFT Engineer

San Jose, CA · On-site

$141K - $226K/yr

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs ...

Broadcom, Inc.

ASIC DFT Engineer

San Jose, CA · On-site

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs ...

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Showing results 41-60

All JobsApd JobsApd Jobs in California

Apd information

See California salary details

$49.8K

$87K

$125.3K

How much do apd jobs pay per year?

As of Aug 6, 2026, the average yearly pay for apd in California is $87,039.00, according to ZipRecruiter salary data. Most workers in this role earn between $72,500.00 and $96,700.00 per year, depending on experience, location, and employer.

What are some common challenges faced by assistant public defenders when managing heavy caseloads, and how can these be addressed?

Assistant Public Defenders (APDs) often handle a large volume of cases simultaneously, which can be challenging in terms of time management and ensuring each client receives quality representation. Balancing court appearances, client meetings, and case preparation requires strong organizational skills and the ability to prioritize tasks efficiently. Many offices support APDs through mentorship programs, regular training, and collaboration with colleagues to share strategies and resources. Building good communication and teamwork with investigators, paralegals, and other attorneys is also essential for managing workloads and delivering effective defense.

What is the difference between Apd vs Speech-Language Pathologist?

AspectApdSpeech-Language Pathologist
Required CredentialsCertificate of Clinical Competence (CCC), state licensureMaster's degree in Speech-Language Pathology, CCC, state licensure
Work EnvironmentSchools, clinics, hospitals, private practiceSchools, healthcare facilities, rehabilitation centers
Industry UsageOften used in educational and clinical settings for auditory processing disordersBroader term covering all speech, language, and communication disorders

Apd (Auditory Processing Disorder) is a specific diagnosis related to difficulties in processing auditory information, often managed by Speech-Language Pathologists (SLPs). SLPs have a broader scope, diagnosing and treating various speech and language issues. While Apd refers to a condition, SLP is the professional role that assesses and treats it.

What is an APD?

APD typically stands for Assistant Police Director or Assistant Police Department, but it can also refer to other roles depending on the context, such as Auditory Processing Disorder in medical fields. In law enforcement, an APD is a high-ranking official responsible for assisting the police director in managing departmental operations, overseeing staff, and implementing policies. Their duties often include administrative leadership, strategic planning, and coordination with other agencies to ensure public safety and effective law enforcement. The specific responsibilities and requirements for APDs may vary by organization and jurisdiction.

What are the key skills and qualifications needed to thrive as an assistant principal, and why are they important?

To thrive as an Assistant Principal, you need a background in education, strong leadership abilities, and a relevant administrative certification or master's degree. Familiarity with student information systems, educational assessment tools, and state and district compliance software is typically required. Excellent communication, conflict resolution, and organizational skills help foster a positive school climate and support both staff and students. These skills and qualifications are vital to effectively manage school operations, uphold academic standards, and ensure a safe, productive learning environment.
What are popular job titles related to Apd jobs in California? For Apd jobs in California, the most frequently searched job titles are:
What job categories do people searching Apd jobs in California look for? The top searched job categories for Apd jobs in California are:
What cities in California are hiring for Apd jobs? Cities in California with the most Apd job openings:
Apd jobs near you
Infographic showing various Apd job openings in California as of August 2026, with employment types broken down into 59% Full Time, 35% Part Time, and 6% Contract. Highlights an 94% In-person, and 6% Remote job distribution, with an average salary of $87,039 per year, or $41.8 per hour.

Manager, Package Design Engineering

Astera Labs

San Jose, CA • On-site

Full-time

Re-posted 12 days ago

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you'll own the end-to-end delivery of advanced IC packaging solutions-from early architecture definition through production ramp-enabling the next generation of AI infrastructure and connectivity products.
As the semiconductor industry races toward chiplet-based architectures, 2.5D/3D integration, and ever-increasing bandwidth demands, packaging has become a critical differentiator. You'll build and mentor a high-performing team while driving cross-functional execution with silicon architecture, SIPI, PCB, validation, manufacturing, and external partners including substrate vendors and OSATs. Your work will directly impact Astera Labs' ability to deliver industry-leading PCIe, CXL, and Ethernet connectivity solutions to the world's most demanding hyperscale and AI customers.
This role offers the opportunity to shape design methodology, establish scalable standards, and enable chip-package-board co-design frameworks across multiple product lines in a fast-moving, innovation-driven environment.
Key Responsibilities
  • Team Leadership & Execution
    • Build, mentor, and scale a high-performing package design engineering team with clear ownership, accountability, and execution flows
    • Establish design templates, standards, and best-known methods (BKMs) across multiple concurrent programs
    • Lead design reviews, audits, and issue resolution through bring-up and production ramp
  • Package Design Delivery
    • Own end-to-end package design execution including FCBGA/FCCSP, monolithic, multi-die, and chiplet-based designs from concept feasibility through tape-out and production
    • Define and review substrate stack-ups, pad stacks, routing strategies, and design constraints to meet electrical, thermal, mechanical, and manufacturability requirements
    • Drive technical tradeoffs across performance, cost, yield, and schedule, ensuring high-quality design closure and on-time delivery
  • Cross-Functional Collaboration
    • Partner with SIPI, silicon architecture, system/board design, and product teams to drive chip-package-board co-design and resolve system-level challenges
    • Collaborate with OSATs and substrate vendors to ensure design feasibility, manufacturability, and alignment with evolving design rules and technology roadmaps
    • Support adoption of advanced packaging technologies such as 2.5D, chiplet, CPO/CPC, and heterogeneous integration platforms
  • Methodology & Automation
    • Develop and scale design methodologies and automation flows to improve efficiency, quality, and repeatability across the organization

Basic Qualifications
  • Bachelor's degree in Electrical Engineering, Materials Science, or related field
  • 10+ years of progressive experience in IC package design using tools such as Cadence Allegro APD/SiP
  • 5+ years of leadership experience managing teams or technical organizations in IC packaging environments
  • Strong hands-on expertise in end-to-end package design with proven delivery of HVM-ready FCBGA/FCCSP packages using Cadence APD tool
  • Experience with high-speed SerDes systems (PCIe Gen5/6/7, CXL, Ethernet 100G/200G/400G+) and advanced nodes (7nm, 5nm, 3nm)
  • Deep understanding of substrate technologies, stack-ups, routing constraints, assembly processes, and SI/PI fundamentals
  • Proven experience working with OSATs and substrate vendors through development and production ramp
  • Experience working with OSATs and substrate vendors through development and production ramp
  • Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration

Preferred Qualifications
  • Master's degree in Electrical Engineering or related field
  • Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration
  • Experience implementing automation, scripting (Python, SKILL, Tcl), or workflow optimization
  • Background in early package feasibility, platform evaluation, and technology roadmap development
  • Familiarity with chip floor planning, architecture, and system-level tradeoffs
  • Exposure to SIPI modeling and analysis, thermal, and mechanical performance considerations

The base salary range is $230,000 USD - $265,000 USD. This position can be hired as a Manager Level or Director Level. Your base salary will be determined based on location, experience, and employees' pay in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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