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Analog Layout Design Jobs (NOW HIRING)

Analog Layout Lead

San Jose, CA · On-site

$236K/yr

Every line of code, every design decision, every breakthrough you help deliver will shape the ... Define and enforce analog layout methodologies, design rules, and best practices across the ...

Analog Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

We are looking for qualified Analog design engineers who have a good understanding of analog ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

$149K/yr

Every line of code, every design decision, every breakthrough you help deliver will shape the ... Define and enforce analog layout methodologies, design rules, and best practices across the ...

Analog Layout Lead

San Jose, CA · On-site

$236K/yr

Every line of code, every design decision, every breakthrough you help deliver will shape the ... Define and enforce analog layout methodologies, design rules, and best practices across the ...

Analog Design Engineer

Irvine, CA · On-site

$110K - $150K/yr

We are looking forImage Sensor Analog Design Engineer for design and development of next generation ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

Sr. Analog Design Engineer

Santa Clara, CA · On-site

$130K - $150K/yr

Description We are looking for qualified Analog circuit design engineers who have a good ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

Sr. Analog Design Engineer

Santa Clara, CA · On-site

$130K - $150K/yr

We are looking for qualified Analog circuit design engineers who have a good understanding of ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

Analog Design Engineer

Irvine, CA · On-site

$110K - $150K/yr

We are looking for Image Sensor Analog Design Engineer for design and development of next ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

We are looking for Image Sensor Analog Design Engineer for design and development of next ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

Analog Design Engineer

Irvine, CA · On-site

$110K - $150K/yr

Description We are looking for Image Sensor Analog Design Engineer for design and development of ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

... design and layout organization. In this role, you will contribute to cutting-edge analog and mixed ... signal IP development, working across complex technologies such as FinFET and deep sub-micron ...

Analog Layout Automation Engineer

San Diego, CA · On-site

$214K/yr

Description As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create ...

Analog Layout Engineer

Santa Clara, CA · On-site

$237K/yr

... design and layout organization. In this role, you will contribute to cutting-edge analog and mixed ... signal IP development, working across complex technologies such as FinFET and deep sub-micron ...

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Analog Layout Design information

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$77K

$186.2K

$203K

How much do analog layout design jobs pay per year?

As of Sep 10, 2026, the average yearly pay for analog layout design in the United States is $186,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $202,000.00 and $202,000.00 per year, depending on experience, location, and employer.

What is analog layout design?

Analog layout design is the process of creating the physical layout of analog integrated circuits (ICs), such as amplifiers, voltage regulators, and data converters. Unlike digital layout, analog layout requires careful placement and routing of components to minimize noise, parasitic effects, and mismatches that can affect circuit performance. Analog layout designers work closely with circuit designers to ensure the chip meets electrical and performance specifications. Precision, symmetry, and matching are critical in analog layouts to achieve high performance and reliability in the final product.

What are the key skills and qualifications needed to thrive as an analog layout designer, and why are they important?

To thrive as an Analog Layout Designer, you need a solid understanding of semiconductor physics, circuit design principles, and experience with analog/mixed-signal layout, typically backed by a degree in electrical engineering or a related field. Proficiency in EDA tools such as Cadence Virtuoso, Mentor Graphics, and DRC/LVS verification tools is essential. Attention to detail, problem-solving skills, and effective communication are standout soft skills for collaborating with circuit designers and ensuring design quality. These competencies are critical for producing reliable, high-performance integrated circuits that meet stringent specifications and industry standards.

What are some common challenges faced by analog layout designers during the tape-out phase, and how can they be addressed?

Analog layout designers often encounter challenges like last-minute design changes, managing parasitic effects, and ensuring layout-versus-schematic (LVS) and design rule check (DRC) compliance during the tape-out phase. Addressing these issues requires close collaboration with circuit designers, proactive communication to anticipate potential changes, and rigorous verification using advanced EDA tools. Staying organized and maintaining clear documentation throughout the design process also helps ensure a smoother tape-out with fewer errors or delays.

What is the difference between Analog Layout Design vs Digital IC Design?

AspectAnalog Layout DesignDigital IC Design
Required SkillsAnalog circuit theory, layout techniques, parasitic managementDigital logic, HDL coding, timing analysis
Work EnvironmentCleanroom, detailed layout work, focus on signal integritySimulation, synthesis, verification, more software-based
Industry UsageSemiconductor manufacturing, RF, analog chipsMicroprocessors, memory, digital systems

Analog Layout Design and Digital IC Design are both essential in semiconductor development but focus on different aspects. Analog layout emphasizes precise circuit placement and parasitic control for analog signals, while digital IC design centers on logic implementation and timing. Understanding these differences helps in choosing the right career path or collaboration focus within the industry.

Are analog layout design engineers in demand?

Analog layout design engineers are in steady demand due to the ongoing need for high-performance analog and mixed-signal integrated circuits in industries such as telecommunications, consumer electronics, and automotive. Skills in CAD tools like Cadence and a strong understanding of semiconductor fabrication processes enhance employability in this field.

Is analog layout design a good career?

Analog layout design is a specialized field within electronics engineering focused on creating physical circuit layouts for analog components. It requires knowledge of semiconductor processes, CAD tools, and attention to detail, often involving collaboration with circuit designers. The profession offers steady demand in industries like telecommunications, consumer electronics, and aerospace, with opportunities for career growth and specialization.

What does an analog layout design do?

An analog layout design involves creating the physical layout of analog circuits on a chip, ensuring proper placement and routing of components like transistors, resistors, and capacitors to meet electrical performance specifications. It requires knowledge of semiconductor fabrication processes and tools such as CAD software to optimize signal integrity, power consumption, and device matching. This role is essential for translating circuit schematics into manufacturable integrated circuits.
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Infographic showing various Analog Layout Design job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 87% Full Time, 9% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $186,238 per year, or $89.5 per hour.

Analog Layout Lead

San Jose, CA • On-site

$236K/yr

Full-time

Medical

Posted 7 days ago


Job description

ABOUT LUMILENS
At Lumilens we are building the critical photonics infrastructure that powers tomorrow's AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.
We're a well-funded startup backed by Mayfield and led by industry's veterans who've built and scaled some of the most transformative technologies in the industry. This isn't incremental innovation, it's a ground-floor opportunity to rethink the optical layer from the silicon up. You'll work alongside a team of world-class engineers solving some of the hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.
If you're looking for mission, momentum, and the chance to make an outsized impact jump on the rocket ship. We're just getting started.
POSITION OVERVIEW
We are seeking an Analog Layout Lead to drive full-custom analog and mixed-signal layout for Lumilens' next-generation silicon platforms. This role will lead complex physical implementation across advanced CMOS nodes, partner closely with circuit design and physical design teams, and establish layout methodologies that ensure performance, reliability, manufacturability, and tape-out readiness across multiple silicon programs.
What You'll Do:
  • Lead full-custom layout of complex analog and mixed-signal blocks, including PLLs, ADCs, DACs, LDOs, bandgaps, and high-speed I/O for custom silicon platforms.
  • Define and enforce analog layout methodologies, design rules, and best practices across the physical design team.
  • Drive parasitic-aware layout strategies to meet stringent noise, matching, signal integrity, and power requirements for mixed-signal designs.
  • Collaborate with circuit designers to translate schematic intent into optimized physical implementations, iterating on layout-versus-schematic and parasitic extraction results.
  • Own physical verification closure, including DRC, LVS, antenna checks, and sign-off readiness across advanced process nodes.
  • Establish floorplanning and integration strategies for analog IP blocks within larger mixed-signal SoC contexts.
  • Provide technical guidance and layout direction to engineers and contractors, reviewing layouts and driving consistency in methodology, quality, and schedule execution.
  • Partner with process technology and design kit teams to evaluate new process nodes, contribute to PDK qualification, and resolve layout-induced performance issues through post-layout simulation analysis.
  • Own long-term physical design roadmaps and methodology investments that scale across multiple silicon programs.

Key Qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience.
  • 8+ years of experience in full-custom analog and mixed-signal layout for production silicon in advanced CMOS process nodes, preferably 28nm or below.
  • 8+ years of hands-on experience with industry-standard layout tools such as Cadence Virtuoso for schematic-driven layout, parasitic extraction, and physical verification.
  • Experience leading layout of high-performance analog blocks such as PLLs, voltage regulators, data converters, or high-speed interfaces from concept through tape-out.
  • Experience defining and implementing layout methodologies for matching, shielding, noise isolation, and signal integrity in mixed-signal environments.
  • Experience collaborating with circuit design teams to interpret simulation requirements and translate them into layout constraints, implementation decisions, and verification closure.
  • Experience managing, mentoring, and reviewing the work of layout engineers while coordinating deliverables with external contractors.

Preferred Skills:
  • Familiarity with post-layout simulation flows, including RC extraction and back-annotated verification using tools such as Spectre or Calibre.
  • Experience contributing to or evaluating process design kits and design rule documentation for new process node bring-up.
  • Experience with analog layout for photonics, AI infrastructure, consumer wearable, mobile, or IoT SoCs where power, area, and reliability constraints are critical.
  • Experience with 3D stacking technologies, advanced packaging layout considerations, or reusable analog layout templates that improve team-wide efficiency and consistency.

Why Join Us?
• Competitive salary commensurate with experience
• Comprehensive benefits package including health insurance
• Professional development opportunities and certification support
• Access to cutting-edge technology and cloud platforms
• Collaborative work environment with cross-functional teams
• Innovate with a Silicon Valley headquartered team, change the world
• Lumilens is an equal opportunity employer. All qualified applicants will receive consideration without regard to race, color, religion, gender, identity, orientation, veteran status, disability, or any other legally protected status.