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Analog Design Manager Jobs in Arizona (NOW HIRING)

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Analog Design Manager information

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$71.8K

$173.6K

$189.2K

How much do analog design manager jobs pay per year?

As of Aug 9, 2026, the average yearly pay for analog design manager in Arizona is $173,553.00, according to ZipRecruiter salary data. Most workers in this role earn between $188,200.00 and $188,200.00 per year, depending on experience, location, and employer.

What are the typical responsibilities of an analog design manager on a daily basis?

An Analog Design Manager typically oversees a team of design engineers, reviews and guides the development of analog and mixed-signal circuits, and ensures that projects meet technical and timeline requirements. Daily activities often include project planning, cross-functional meetings with layout engineers and verification teams, and hands-on technical problem-solving. Managers may also be responsible for mentoring junior staff, managing resource allocation, and reporting progress to upper management. This role requires a balance between technical oversight and people management to ensure the team's success and high-quality deliverables.

What does an analog design manager do?

An Analog Design Manager leads a team of engineers in designing, developing, and optimizing analog and mixed-signal circuits for various applications. They oversee project timelines, collaborate with cross-functional teams, and ensure the delivery of high-performance design solutions. Their role involves technical guidance, mentorship, and problem-solving to meet product specifications and industry standards. Additionally, they stay updated on emerging technologies to drive innovation in analog circuit design.

What are the key skills and qualifications needed to thrive as an analog design manager?

To thrive as an Analog Design Manager, you need a strong background in analog and mixed-signal circuit design, typically supported by a degree in electrical engineering and relevant industry experience. Familiarity with EDA tools such as Cadence, SPICE simulators, and a solid understanding of industry standards are essential, with management or project leadership certifications being advantageous. Effective communication, leadership, and team management abilities distinguish top performers in this position. These skills are crucial for ensuring successful project execution, innovation, and collaboration in the fast-paced semiconductor industry.

What are the most commonly searched types of Analog Design jobs in Arizona? The most popular types of Analog Design jobs in Arizona are:
What job categories do people searching Analog Design Manager jobs in Arizona look for? The top searched job categories for Analog Design Manager jobs in Arizona are:
What cities in Arizona are hiring for Analog Design Manager jobs? Cities in Arizona with the most Analog Design Manager job openings:
Infographic showing various Analog Design Manager job openings in Arizona as of August 2026, with employment types broken down into 86% Full Time, 12% Part Time, and 2% Contract. Highlights an 84% Physical, 3% Hybrid, and 13% Remote job distribution, with an average salary of $173,553 per year, or $83.4 per hour.

Principal Engineer, Digital Design Engineer (AI/ML)

Analogdevices

Chandler, AZ

$198K/yr

Full-time

Re-posted 28 days ago


Job description

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.comand on LinkedIn and X.

As a Principal Digital Design Engineer, you will lead the architecture and implementation of complex digital subsystems within ADI's mixed-signal and power management ICs. You will drive the adoption of AI/ML techniques to transform design automation, optimization, and productivity across the digital design flow. Your work will span multiple business units and directly shape how ADI integrates advanced digital functionality into next-generation products.

Key Responsibilities
  • Drive adoption of AI/ML methodologies to optimize synthesis, timing closure, power estimation, and design space exploration
  • Define and lead digital architecture for complex SoCs and mixed-signal ICs, including control logic, digital interfaces, and on-chip processing
  • Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power targets
  • Own the synthesis-to-signoff flow including synthesis with timing and placement constraints (Genus), STA and power analysis (Tempus), and logical equivalence checking (Conformal)
  • Lead architecture and design reviews, assessing trade-offs across timing, area, power, and testability
  • Influence design flows, IP reuse strategies, and product roadmaps across multiple projects
  • Collaborate with analog design teams to define and integrate digital-analog interfaces and control architectures
Required Skills and Experience
  • MSEE or MSCE with 10+ years of digital IC design experience, or PhD with 8+ years (BSEE/BSCE with equivalent depth considered)
  • Expert-level RTL design in Verilog/SystemVerilog with proven track record of complex digital subsystem delivery
  • Track record of leading digital designs from architecture through tape-out, silicon validation, and production release
  • Strong scripting skills (Python, Tcl, shell) with experience applying AI/ML techniques to enhance productivity
  • Deep knowledge of synthesis, static timing analysis, DFT (scan, ATPG, BIST), and clock domain crossing methodologies
  • Proficiency with Cadence digital design tools: Genus, Innovus, Tempus, Conformal
  • Excellent presentation, technical writing, and communication skills
Preferred Qualifications
  • Working knowledge of place-and-route (Innovus), floorplanning, and physical-aware design techniques
  • Experience with low-power design techniques including multi-voltage domains, power gating, and UPF
  • Familiarity with digital interfaces (I2C, SPI, UART) and mixed-signal SoC integration
  • Strong analytical and problem-solving abilities
  • Ability to work effectively in a collaborative team environment
Technical Scope
  • Development and deployment of AI/ML-driven workflows that measurably improve design quality, turnaround time, or coverage
  • Full digital subsystem architecture ownership from specification through silicon bring-up and production validation
  • Clock domain crossing analysis, lint, and formal verification for multi-clock digital architectures
  • DFT strategy and implementation including scan insertion, ATPG pattern generation, and fault coverage closure
Collaboration and Impact
  • Partner with analog design, verification, and applications teams to define digital control architectures that meet system-level requirements
  • Champion AI/ML-driven improvements to digital design workflows, sharing results and best practices across teams
  • Contribute to organizational knowledge through design reviews and cross-team technical forums

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law.

Job Req Type: ExperiencedRequired Travel: NoShift Type: 1st Shift/Days