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Amd Physical Design Engineer Jobs (NOW HIRING)

Value Innovation Labs

Physical Design Engineer

Sunnyvale, CA · On-site

$161K - $166K/yr

Physical Design Engineer - 3D-IC Location: Sunnyvale, CA Work Arrangement: Hybrid Experience: 5-10 Years Employment Type: Full-Time Job Summary We are seeking an experienced Physical Design Engineer ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

iFlow Inc

Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

Physical Design Engineer Location:Sunnyvale, CA OR Austin,TX Duration: Long term experience: 5-18 years only ( No 18+ years profile) Job Overview: We are looking for a highly skilled Physical Design ...

Swift Hire LLC

Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Job Title- Physical Design Engineer Location - San Jose, CA (Onsite) Duration - 6+ months * Good understanding of Cadence tools (Innovous, Quantus, Voltus). * Deep knowledge about industry standards ...

Conductor

Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

We're looking for physical design engineers to help manage and execute the physical design process for the various dies that comprise our A-0 and A-1 systems. This will involve deciding what to do in ...

Ambarella

$140K - $156K/yr

The Physical Design Engineer willbe an integral part of the physical design team with all aspects of physical design implementation and verification tasks for Ambarella's cutting edgelow powerAISoC ...

AIT Global, Inc.

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

Job Title: Physical Design Engineer Location: San Francisco, CA (Bay Area) * Good understanding of Cadence tools (Innovous, Quantus, Voltus). (Must) * Deep knowledge about industry standards in ...

Apple

Physical Design Engineer

Cupertino, CA

$129K - $225K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Generate ...

Apple

Physical Design Engineer

Beaverton, OR

$184K - $324K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$129K - $225K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Bodega Bay, CA · On-site

$150K - $277K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Altera Corporation

Physical Design Engineer

San Jose, CA · On-site

$118K - $169K/yr

About the Role As a Physical Design Engineer at Altera, you will contribute to the physical implementation of FPGA/SoC designs, working with experienced engineers across the backend design flow from ...

Apple

Physical Design Engineer

Beaverton, OR · On-site

$184K - $324K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Beaverton, OR · On-site

$184K - $324K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Altera

Physical Design Engineer

San Jose, CA · On-site

$118K - $169K/yr

About the Role As a Physical Design Engineer at Altera, you will contribute to the physical implementation of FPGA/SoC designs, working with experienced engineers across the backend design flow from ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$129K - $225K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

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Amd Physical Design Engineer information

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$95K

$141.5K

How much do amd physical design engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for amd physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Amd Physical Design Engineer jobs?

For Amd Physical Design Engineer jobs, the most frequently searched job titles are:

Infographic showing various Amd Physical Design Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 78% Full Time, 17% Part Time, 3% Contract, and 1% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

Physical Design Engineer

Sunnyvale, CA • On-site

Value Innovation Labs
See more jobs at Value Innovation Labsexternal

$161K - $166K/yr

Other

Posted 4 days ago

Job description

Physical Design Engineer – 3D-IC

Location: Sunnyvale, CA

Work Arrangement: Hybrid

Experience: 5–10 Years

Employment Type: Full-Time

Job Summary

We are seeking an experienced Physical Design Engineer – 3D-IC to join our semiconductor engineering team. The ideal candidate will have strong hands-on experience in ASIC/SoC Physical Design, including complete RTL-to-GDSII implementation, timing and physical signoff, and advanced-node tape-outs.

The candidate should have experience working with 5nm/3nm/2nm technologies, advanced physical design methodologies, and preferably 3D-IC, multi-die, or heterogeneous integration. Strong scripting skills, particularly Tcl, are required for methodology development and design automation.

Key ResponsibilitiesFull-Chip Physical Design
  • Own and execute the RTL-to-GDSII physical design flow from synthesis through final signoff.
  • Perform physical-aware synthesis, floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.
  • Drive design implementation to achieve timing, power, area, and quality-of-results (QoR) targets.
  • Perform timing closure and implement necessary ECOs throughout the design cycle.
3D-IC & Multi-Die Implementation
  • Support physical implementation of 3D-IC, 2.5D, heterogeneous integration, and multi-die architectures.
  • Perform TSV (Through-Silicon Via) planning and analyze die-to-die interconnect considerations.
  • Work with advanced packaging and 3D integration teams to address physical design challenges.
  • Analyze and resolve IR drop, electromigration (EM), thermal, and signal-integrity issues across multi-die designs.
Timing, Power & Signoff
  • Perform static timing analysis (STA) and drive timing closure for high-performance designs operating at 1GHz+.
  • Develop and execute MCMM/MMCM implementation and signoff strategies.
  • Analyze and resolve setup/hold violations, clock skew, crosstalk, and signal-integrity issues.
  • Implement low-power designs using UPF/CPF and support power-intent verification.
  • Perform or support IR-drop and EM analysis and physical signoff.
Methodology & Automation
  • Develop and maintain physical design methodologies and flows.
  • Create automation and productivity solutions using Tcl (mandatory), Python, and/or Perl.
  • Automate repetitive implementation, analysis, reporting, and signoff tasks.
  • Collaborate with IP, RTL, STA, DFT, packaging, foundry, and EDA teams to resolve implementation challenges.
  • Work with foundry and IP partners to ensure technology and design requirements are met.
Required Qualifications
  • 5–10 years of hands-on experience in ASIC/SoC Physical Design.
  • Multiple successful full-cycle tape-outs from RTL through GDSII.
  • Experience with advanced semiconductor process nodes, preferably 5nm, 3nm, or 2nm.
  • Strong understanding of the complete RTL-to-GDSII implementation flow.
  • Strong experience with floorplanning, placement, CTS, routing, optimization, and timing closure.
  • Hands-on experience with MCMM/MMCM, STA, signal integrity, IR drop, and EM analysis.
  • Experience implementing high-frequency designs (1GHz+).
  • Experience with low-power design methodologies using UPF/CPF.
  • Strong hands-on experience with one or more industry-standard EDA flows:
  • Cadence: Innovus, Tempus, Voltus
  • Synopsys: ICC2, PrimeTime
  • Strong Tcl scripting skills – mandatory.
  • Proficiency in Python and/or Perl is highly desirable.
  • Strong problem-solving and debugging skills with the ability to work across multiple design disciplines.

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