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5G Rf Optimization Engineer Jobs in Oregon (NOW HIRING)

Intel

Analog Engineer

Hillsboro, OR · On-site

$141K - $269K/yr

Collaborating with cross-functional teams, you will play a critical role in optimizing performance ... RF or millimeter-wave circuits. - Strong understanding of power delivery networks (PDN) and ...

Qorvo, Inc.

Process Development Engineering Intern

Bend, OR · On-site

$31 - $42/hr

Recipe Optimization: Troubleshoot fabrication processes and optimize equipment recipes for physical ... We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure ...

Qorvo, Inc.

Process Development Engineering Intern

Bend, OR · On-site

$31 - $42/hr

Recipe Optimization: Troubleshoot fabrication processes and optimize equipment recipes for physical ... We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure ...

Qorvo, Inc.

Process Engineering Intern

Hillsboro, OR

$31 - $42/hr

Process troubleshooting and recipe optimization. * Experimental design and execution of a fab ... We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure ...

Qorvo, Inc.

Process Engineering Intern

Hillsboro, OR · On-site

$31 - $42/hr

Process troubleshooting and recipe optimization. * Experimental design and execution of a fab ... We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure ...

Intel

Semiconductor Device Modeling Engineer

Hillsboro, OR · On-site

$149K - $284K/yr

As a member of CDMG, you will be at the forefront of co-optimizing Intel's state-of-the-art process ... Experience in test automation and RF/noise/reliability tests is a plus. * Understanding of Aging ...

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5G Rf Optimization Engineer information

See Oregon salary details

$39.1K

$124.4K

$193.5K

How much do 5g rf optimization engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for 5g rf optimization engineer in Oregon is $124,422.00, according to ZipRecruiter salary data. Most workers in this role earn between $103,100.00 and $147,000.00 per year, depending on experience, location, and employer.

What does a 5G RF Optimization Engineer do?

A 5G RF Optimization Engineer is responsible for ensuring optimal performance of 5G wireless networks by analyzing and improving radio frequency (RF) parameters. They use specialized tools to monitor network quality, identify coverage gaps, and resolve issues related to signal strength, interference, and data throughput. Their work involves tuning network equipment, conducting drive tests, and collaborating with other engineers to implement solutions that enhance user experience and network efficiency.

What are the key skills and qualifications needed to thrive as a 5G RF Optimization Engineer, and why are they important?

To thrive as a 5G RF Optimization Engineer, you need a solid background in wireless communications, RF engineering principles, and a relevant engineering degree. Expertise in RF planning tools, drive test equipment, and knowledge of system optimization platforms such as TEMS, Atoll, or Actix, along with relevant certifications like CCNA or 5G-specific credentials, are typically required. Strong analytical thinking, troubleshooting abilities, and effective communication skills help you collaborate with cross-functional teams and resolve network issues efficiently. These competencies are crucial for ensuring optimal network performance, customer satisfaction, and successful deployment of advanced 5G technologies.

What are some common challenges faced by a 5G RF Optimization Engineer when deploying new sites, and how are they typically addressed?

A 5G RF Optimization Engineer often encounters challenges such as interference management, handover optimization, and ensuring consistent coverage in dense urban environments during new site deployments. These challenges are typically addressed through detailed drive testing, network parameter tuning, and close collaboration with network planners and field teams. Engineers also utilize advanced software tools to analyze performance metrics and implement solutions like antenna tilt adjustments, frequency planning, and power optimization to enhance network quality.

What is the difference between 5G Rf Optimization Engineer vs RF Network Engineer?

Aspect5G Rf Optimization EngineerRF Network Engineer
Primary FocusOptimizing 5G radio frequency performance and coverageDesigning, deploying, and maintaining RF networks
CertificationsRF, wireless, or telecom certifications, often including 5G-specific trainingSimilar certifications, with emphasis on RF and network design
Work EnvironmentField testing, site surveys, and network optimization in telecom companiesNetwork planning, deployment, and troubleshooting in telecom or service providers

The 5G Rf Optimization Engineer specializes in fine-tuning 5G radio networks to ensure optimal performance, coverage, and capacity. In contrast, the RF Network Engineer focuses on designing and maintaining RF networks, including 4G and 5G, across various stages. Both roles require similar certifications and often work within the same industry environments, but their core responsibilities differ in scope and focus.

What are popular job titles related to 5G Rf Optimization Engineer jobs in Oregon?

For 5G Rf Optimization Engineer jobs in Oregon, the most frequently searched job titles are:

What job categories do people searching 5G Rf Optimization Engineer jobs in Oregon look for?

The top searched job categories for 5G Rf Optimization Engineer jobs in Oregon are:

5G Rf Optimization Engineer jobs near you
Infographic showing various 5G Rf Optimization Engineer job openings in Oregon as of September 2026, with employment types broken down into 93% Full Time, and 7% Contract. Highlights an 86% In-person, 7% Hybrid, and 7% Remote job distribution, with an average salary of $124,422 per year, or $59.8 per hour.

Analog Engineer

Hillsboro, OR • On-site

Intel
Manufacturing • 10K+ employees
Learn more about Intelexternal

$141K - $269K/yr

Full-time

Medical, Retirement, PTO

Re-posted 27 days ago

Key responsibilities

  • Design, develop, and implement analog circuits and mixed-signal IPs, including ADCs, DACs, voltage regulators, and high-speed I/O interfaces.

  • Perform circuit-level design, simulation, and optimization to meet power, performance, area, timing, and yield requirements.

  • Collaborate with architecture and layout teams to design circuits that maximize functionality, robustness, and electrical capabilities.

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

Job description

Job Details:Job Description: 

The Role and Impact
Join Intel's Advanced Design Foundational IP Organization (AD-FIP) within the Design Technology Platform (DTP), a team that is pivotal in shaping the future of analog and mixed-signal IC design. As an Analog Circuit Design Engineer, you will be at the forefront of designing and developing cutting-edge analog circuits in advanced process nodes. Your work will directly impact Intel's ability to deliver the best-in-class foundational IP and product designs that drive innovation across client, server, and networking technologies. Collaborating with cross-functional teams, you will play a critical role in optimizing performance, power, area, and yield of circuits while pushing the boundaries of what is possible in semiconductor technology.
Key Responsibilities
- Design, develop, and implement analog circuits and mixed-signal IPs, including ADCs, DACs, voltage regulators, and high-speed I/O interfaces.
- Perform circuit-level design, simulation, and optimization to meet power, performance, area, timing, and yield requirements.
- Create and validate floorplans, extract chip parameters, and simulate analog behavior models to ensure robust designs.
- Develop test plans for design verification and evaluate test results to meet specification requirements.
- Collaborate with architecture and layout teams to design circuits that maximize functionality, robustness, and electrical capabilities.
- Conduct tape-out activities for analog and mixed-signal circuits, ensuring successful silicon implementation.
- Analyze and resolve performance and circuit-related issues during design and post-silicon validation phases.
- Serve as a technical interface to process technology, IP engineers, and product teams, leveraging design insights to influence future process node development.

Qualifications:

Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 4+ years of experience in analog and mixed-signal circuit design; or Master's degree with 3+ years of experience; or PhD with 1+ years of experience.
- Expertise in analog circuit design, simulation, and verification.
- Proficiency in CMOS technologies and layout understanding for analog circuits.
- Experience with tape-out processes for analog mixed-signal circuits, including ADCs and DACs.
- Knowledge of SoC analog layout design checks and methodologies.
Preferred Qualifications
- Advanced knowledge of high-speed parallel or serial I/O links, clock distribution, or voltage regulator design.
- Experience with PLLs, bandgap references, inductors, transmission lines, and RF or millimeter-wave circuits.
- Strong understanding of power delivery networks (PDN) and integrated power regulators.
- Proven ability to collaborate across teams and influence decisions related to process technology and product development.
Come be a part of Intel's mission to shape the future of technology. Apply today to join a team where innovation, collaboration, and excellence drive the creation of transformative products.

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, AustinPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

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Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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