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60 Lightmatter Physical Design Engineer Jobs Hiring Near You

Lightmatter

Foundry Engineer

Mountain View, CA · On-site

... the design process * Develop silicon technology and capability roadmap to support Lightmatter ... Bachelor's in Electrical Engineering, Physics, Materials Engineering/Science, Mechanical ...

Lightmatter

Signal Integrity Engineer

Mountain View, CA · On-site

$157K - $176K/yr

Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant ... Participate in signal integrity design reviews, presenting findings and suggesting creative ...

Lightmatter

Analog/Mixed Signal Architect

Boston, MA · On-site

$149K - $216K/yr

The selected candidate will partner with internal engineering teams at Lightmatter to deliver groundbreaking products to the market. In this role, you will contribute to the design and development of ...

Lightmatter

Photonics Architect

Boston, MA · On-site

$150K - $220K/yr

Work closely with the photonic engineering design team to provide the performance, power, and area ... Lightmatter recruits, employs, trains, compensates, and promotes regardless of race, religion ...

Lightmatter

The selected candidate will partner with internal engineering teams at Lightmatter to deliver groundbreaking products to the market. In this role, you will contribute to the design and development of ...

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Infographic showing various Physical Design Engineer job openings at Lightmatter in the United States as of August 2026, with employment types broken down into 99% Full Time, and 1% Temporary. Highlights an 99% Physical, and 1% Hybrid job distribution.

Sr. Design for Test (DFT) Engineer

Lightmatter

Mountain View, CA • On-site

Full-time

Re-posted 6 days ago

Job description

 As a Design for Test Engineer you will work closely with all disciplines involved in chip design and product operations to design, validate, and deploy test solutions for digital, analog, and photonic logic. You will be involved in a variety of tasks including logic design, validation and logic simulations, scripting, timing closure, post-silicon planning and bring up, and bringing products to market.

Responsibilities

  • Create new chip, module, and system-level DFT solutions for our highly integrated photonics-based AI platform
  • Develop and deploy DFT methodologies for our next generation products
  • Provide architecture for integrated electronics/analog/digital test including ATPG and boundary scan
  • Work with RTL designers to define front-end integration
  • Work with physical-design engineers to provide backend integration
  • Create automated flow that can scale with the team and company
  • Support initial silicon bring-up through debug 
  • Validate DFT implementation and requirements
  • Proactively solve problems while managing deliverables in a fast-paced, evolving environment.

Minimum Qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
  • At least 5 years of industry experience working on DFT-related activities for advanced ASIC designs
  • Proven experience in pre-silicon design activities
  • Work independently on daily tasks and projects, while seeking guidance for new and unfamiliar assignments.
  • Experience with scripting languages such as Python or TCL
  • Solid understanding of DFT concepts such as Scan, ATPG, memory test, and JTAG
  • Knowledge of Basic SoC Architecture and HDL languages like Verilog
  • Experience working with commercial EDA DFT tools on MBIST, ATPG, and Boundary Scan. 

Preferred Qualifications:

  • Master degree in Electrical Engineering, Computer Engineering, or related field with 3+ years of industry experience working on ASIC designs with multiple production-quality ASIC tapeouts
  • Prior experience working on DFT related tasks in either logic design, validation, implementation or pattern generation and coverage analysis
  • Understanding of industry standards and practices in DFT, including JTAG/BSCAN, at-speed Scan-ATPG, MBIST, and trade-offs between test quality and test time
  • Ability to conduct experiments during silicon debug, gathering and analyzing data, and utilize scripting to support efficient handling of ATE data 
  • Understanding of Timing, Physical Design, and Power impact of DFT structures
  • Strong teamwork and communication skills with the ability to collaborate with multiple functional teams across a variety of fields

Apply