Intel's AI SoC organization is driving innovation in next-generation ASICs for AI applications ... Collaborate with design and simulation teams to identify corner cases and complement dynamic ...

60 Intel Design Verification Engineer Jobs Hiring in CA
Intel's AI SoC organization is driving innovation in next-generation ASICs for AI applications ... Collaborate with design and simulation teams to identify corner cases and complement dynamic ...
Your efforts will directly impact Intel's ability to maintain technological leadership in the ... Familiarity with physical verification techniques, including DRC, LVS, and density/fill modules.
Your efforts will directly impact Intel's ability to maintain technological leadership in the ... Familiarity with physical verification techniques, including DRC, LVS, and density/fill modules.
EDA Tools SW Engineer
Santa Clara, CA · Hybrid
$173K - $330K/yr
At Intel, Design Technology Platforms (DTP) is one of the key pillars enabling Intel to deliver ... Experience with Test chip physical verification and tape-in * Intel and/or external foundry process ...
EDA Tools SW Engineer
Santa Clara, CA · Hybrid
$173K - $330K/yr
At Intel, Design Technology Platforms (DTP) is one of the key pillars enabling Intel to deliver ... Experience with Test chip physical verification and tape-in * Intel and/or external foundry process ...
Senior Density Fill Development Engineer
$122K - $168K/yr
The Role and Impact Join Intel's Design Technology Platform (DTP) organization and become an ... Minimum 5 years of hands-on experience with at least one industry-standard physical verification ...
Senior Density Fill Development Engineer
$122K - $168K/yr
The Role and Impact Join Intel's Design Technology Platform (DTP) organization and become an ... Minimum 5 years of hands-on experience with at least one industry-standard physical verification ...
Analog Circuit Design Engineer
Santa Clara, CA · On-site
$122K - $232K/yr
About Intel: At Intel, we strive to create innovative technologies that shape the future of ... Author microarchitecture specifications, test plans, and documentation for design verification and ...
Analog Circuit Design Engineer
Santa Clara, CA · On-site
$122K - $232K/yr
About Intel: At Intel, we strive to create innovative technologies that shape the future of ... Author microarchitecture specifications, test plans, and documentation for design verification and ...
Analog Circuit Design Engineer
Folsom, CA · On-site
$122K - $232K/yr
About Intel: At Intel, we strive to create innovative technologies that shape the future of ... Author microarchitecture specifications, test plans, and documentation for design verification and ...
Analog Circuit Design Engineer
Folsom, CA · On-site
$122K - $232K/yr
About Intel: At Intel, we strive to create innovative technologies that shape the future of ... Author microarchitecture specifications, test plans, and documentation for design verification and ...
Senior EDA Tools Software Engineer
$143K - $189K/yr
You will work directly with chassis architecture, RTL design, verification, and SOC integration ... Benefits at Intel Our total rewards package goesabove and beyondjust a paycheck. Whetheryou ...
Senior EDA Tools Software Engineer
$143K - $189K/yr
You will work directly with chassis architecture, RTL design, verification, and SOC integration ... Benefits at Intel Our total rewards package goesabove and beyondjust a paycheck. Whetheryou ...
About the Team Intel is seeking a motivated mid-level CAD/EDA Software Engineer to join the Silicon ... Work closely with the tool lead, architecture, RTL design, verification, and SoC integration teams ...
About the Team Intel is seeking a motivated mid-level CAD/EDA Software Engineer to join the Silicon ... Work closely with the tool lead, architecture, RTL design, verification, and SoC integration teams ...
Semiconductor Device Modeling Engineer
Santa Clara, CA · On-site
$128K - $245K/yr
DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services that allow Intel Foundry customers to deliver winning products to the marketplace. Your work will ...
Semiconductor Device Modeling Engineer
Santa Clara, CA · On-site
$128K - $245K/yr
DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services that allow Intel Foundry customers to deliver winning products to the marketplace. Your work will ...
Analog Engineer
$237K/yr
The Role and Impact Join Intel's Advanced Design Foundational IP Organization (AD-FIP) within the ... Develop test plans for design verification and evaluate test results to meet specification ...
Analog Engineer
$237K/yr
The Role and Impact Join Intel's Advanced Design Foundational IP Organization (AD-FIP) within the ... Develop test plans for design verification and evaluate test results to meet specification ...
Intel is a company of bold and curious inventors and problem solvers who create some of the most ... Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.
Intel is a company of bold and curious inventors and problem solvers who create some of the most ... Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.
About the Team Intel is seeking a motivated mid-level CAD/EDA Software Engineer to join the Silicon ... Work closely with the tool lead, architecture, RTL design, verification, and SoC integration teams ...
About the Team Intel is seeking a motivated mid-level CAD/EDA Software Engineer to join the Silicon ... Work closely with the tool lead, architecture, RTL design, verification, and SoC integration teams ...
Semiconductor Device Modeling Engineer
Santa Clara, CA · On-site
$149K - $284K/yr
DE is a key pillar in enabling Intel to deliver design, development, and manufacturing services ... As a Semiconductor Device Modeling Engineer, you will be responsible for characterizing device ...
Semiconductor Device Modeling Engineer
Santa Clara, CA · On-site
$149K - $284K/yr
DE is a key pillar in enabling Intel to deliver design, development, and manufacturing services ... As a Semiconductor Device Modeling Engineer, you will be responsible for characterizing device ...
Director, Engineering
Folsom, CA · On-site
Physical Design and Implementation Lead, Memory PHY IP (DDR/LPDDR)Intel is seeking an experienced ... Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product ...
Director, Engineering
Folsom, CA · On-site
Physical Design and Implementation Lead, Memory PHY IP (DDR/LPDDR)Intel is seeking an experienced ... Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product ...
Senior EDA Tools Software Engineer
Santa Clara, CA · On-site
$143K - $189K/yr
You will work directly with chassis architecture, RTL design, verification, and SOC integration ... Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole ...
Senior EDA Tools Software Engineer
Santa Clara, CA · On-site
$143K - $189K/yr
You will work directly with chassis architecture, RTL design, verification, and SOC integration ... Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole ...
Staff Semiconductor Device Modeling Engineer
Santa Clara, CA · Hybrid
$149K - $284K/yr
Business Group You will be joining Intel's Design Technology Platform (DTP) organization, a ... Bachelor's degree in Electrical Engineering or a related discipline with 6+ years of industry ...
Staff Semiconductor Device Modeling Engineer
Santa Clara, CA · Hybrid
$149K - $284K/yr
Business Group You will be joining Intel's Design Technology Platform (DTP) organization, a ... Bachelor's degree in Electrical Engineering or a related discipline with 6+ years of industry ...
Director, Engineering
Santa Clara, CA · On-site
Physical Design and Implementation Lead, Memory PHY IP (DDR/LPDDR)Intel is seeking an experienced ... Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product ...
Director, Engineering
Santa Clara, CA · On-site
Physical Design and Implementation Lead, Memory PHY IP (DDR/LPDDR)Intel is seeking an experienced ... Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product ...
Director, Engineering
Folsom, CA · On-site
$221 - $361/hr
Physical Design and Implementation Lead, Memory PHY IP (DDR/LPDDR) Intel is seeking an experienced ... Power integrity * Physical verification * Design signoff * Lead delivery of high-speed PHY ...
Director, Engineering
Folsom, CA · On-site
$221 - $361/hr
Physical Design and Implementation Lead, Memory PHY IP (DDR/LPDDR) Intel is seeking an experienced ... Power integrity * Physical verification * Design signoff * Lead delivery of high-speed PHY ...
Director, Engineering
Folsom, CA · On-site
Physical Design and Implementation Lead, Memory PHY IP (DDR/LPDDR) Intel is seeking an experienced ... integrity oPhysical verification oDesign signoff • Lead delivery of high-speed PHY ...
Director, Engineering
Folsom, CA · On-site
Physical Design and Implementation Lead, Memory PHY IP (DDR/LPDDR) Intel is seeking an experienced ... integrity oPhysical verification oDesign signoff • Lead delivery of high-speed PHY ...
EDA Design Flow Development Engineer
Folsom, CA · On-site
$141K - $269K/yr
The Role and Impact Join Intel in shaping the future of technology. As an EDA Tools Hardware ... verification. The engineer will work closely with circuit design, physical design, package ...
EDA Design Flow Development Engineer
Folsom, CA · On-site
$141K - $269K/yr
The Role and Impact Join Intel in shaping the future of technology. As an EDA Tools Hardware ... verification. The engineer will work closely with circuit design, physical design, package ...
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Full-time
Medical, Retirement, PTO
Re-posted 2 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 159 rated electronics manufacturers
Job description
Job Description:
Intel's AI SoC organization is driving innovation in next-generation ASICs for AI applications across edge and cloud. As a Senior Formal Verification Engineer, you will play a critical role in ensuring the functional correctness of complex digital designs using advanced formal methods. This position offers the opportunity to work on cutting-edge technology and shape verification strategies for AI SoCs.
Key Responsibilities
- Own formal verification strategy and execution for complex SoC IP blocks and subsystems.
- Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and industry-standard formal tools.
- Write and review formal properties, constraints, and coverage goals to achieve exhaustive verification.
- Collaborate with design and simulation teams to identify corner cases and complement dynamic verification.
- Drive formal sign-off, including convergence analysis and coverage closure.
- Contribute to pre-silicon verification, chip bring-up, and post-silicon debug support.
- Mentor junior engineers and establish best practices for formal verification methodology
Additional Responsibilities
- Define and develop scalable, reusable verification plans for block, subsystem, and SoC levels.
- Execute verification plans and run emulation and system simulation models to validate design, analyze power/performance, and uncover bugs.
- Debug and root-cause issues in the presilicon environment; implement corrective measures.
- Collaborate with architects, RTL developers, and physical design teams to improve verification of complex features.
- Document test plans and lead technical reviews with design and architecture teams.
- Incorporate and execute security verification activities within regression and debug tests.
- Maintain and enhance existing functional verification infrastructure and methodology.
- Apply learnings from post-silicon validation to improve coverage and quality for future products.
Qualifications:
Minimum Qualifications
Basic Qualifications
• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science with 10+ years of related experience.
• 7+ years of experience in ASIC/SoC verification with at least 3+ years focused on formal verification.
Preferred Qualifications
• Expertise in formal verification methodologies and tools (e.g., JasperGold, VC Formal, Questa Formal).
• Strong knowledge of System Verilog Assertions (SVA) and property-based verification.
• Deep understanding of digital design concepts, clock domain crossings, and low-power design techniques.
• Familiarity with UVM-based simulation environments and how formal complements dynamic verification.
• Scripting skills (Python, TCL, Perl) for automation and flow optimization.
• Ability to lead projects, work cross-functionally, and deliver under tight schedules.
• Strong analytical skills, attention to detail, and a collaborative mindset.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Folsom
Additional Locations:
US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, Austin
Business group:
Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968