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Astera Labs

60 Astera Labs Product Applications Engineer Jobs Hiring Near You

Astera Labs

Performance Engineer

San Jose, CA · On-site

... and product decisions - and fuel the marketing narrative that positions Astera Labs at the center ... Share infrastructure and playbooks with the Product Applications team to accelerate customer ...

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Infographic showing various Product Applications Engineer job openings at Astera Labs in the United States as of August 2026, with employment types broken down into 100% Full Time. Highlights an 95% Physical, 2% Hybrid, and 3% Remote job distribution.

Principal Product Applications Engineer

Astera Labs

San Jose, CA • On-site

$165K - $210K/yr

Full-time

Posted 9 days ago

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is redefining the fabric of AI infrastructure with our Scorpio Smart Fabric Switches - purpose-built silicon that connects GPUs, CPUs, and accelerators at rack scale. As a Principal Product Applications Engineer on the Scorpio team, you will be the technical face of our switching portfolio to the world's leading hyperscalers, AI system builders, and platform partners, guiding them from first evaluation through production deployment.
This is a high-impact, customer-facing role at the center of one of the fastest-growing categories in semiconductors. You will lead customer system design-in and Scorpio-related debug, develop customer-facing collateral, lead cross-functional Scorpio-related initiatives, and drive and validate new features across PCIe Gen 6 / Gen 7 & UALink platforms - directly influencing the roadmap of a hyper-growth company powering the next generation of AI compute.
Key Responsibilities
  • Customer Enablement
    • Lead technical engagements with hyperscalers, ODMs, and AI system partners from architecture discussions through design-in and evaluation
    • Own on-site and remote bring-up, debug, and performance tuning of Scorpio-based platforms at customer sites
    • Translate customer requirements into actionable feedback for product, silicon, and firmware teams
  • Post-Silicon Validation & System Integration
    • Influence post-silicon validation plans and execute system-level integration on next-generation switching platforms
    • Debug complex multi-domain issues spanning protocol (UALink, UCIe, PCIe Gen 6/7), signal integrity, firmware, and software stacks
    • Partner with hardware, firmware, and SI/PI teams to root-cause issues and deliver production-ready solutions
  • Technical Leadership & Cross-Functional Influence
    • Serve as the go-to Scorpio applications expert across sales, marketing, product, and engineering
    • Mentor junior applications engineers and represent Astera Labs at industry forums, standards bodies, and customer executive reviews
    • Author white papers, technical collateral, and training materials that scale the team's impact

Basic Qualifications
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
  • 8+ years of experience in product applications, systems engineering, or post-silicon validation on high-speed connectivity or networking silicon
  • Strong understanding of the physical layer and high-speed serial interfaces (PCIe, Ethernet, UALink, UCIe, or similar)
  • Hands-on experience with lab bring-up, debug, and system-level integration - including scopes, BERTs, and protocol analyzers
  • Proven track record engaging directly with hyperscaler, cloud, or Tier-1 OEM/ODM customers on complex technical deployments
  • Excellent communication skills with the ability to translate deep technical detail into clear customer-facing narratives

Preferred Qualifications
  • MS or PhD in Electrical Engineering, Computer Engineering, or a related field
  • Direct experience with PCIe Gen 6 / Gen 7, UALink, or UCIe protocols and compliance testing
  • Familiarity with AI/ML rack-scale architectures, GPU fabrics, and accelerator interconnects
  • Scripting and automation experience (Python, shell) for validation and diagnostics
  • Background contributing to standards bodies (PCI-SIG, UALink Consortium, UCIe) or authoring technical publications

Salary range is $165,000 to $210,000 CAN depending on experience, level, and business need. This role may be eligible for discretionary bonuses, incentives, and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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