... designed IPs. Engage in design specification development by participating in discussions on ... Proficiency in Object Oriented Programming, Verilog, System Verilog, UVM, SVA and functional ...

60 Sva Packaging Designer Jobs Hiring Near You
... designed IPs. Engage in design specification development by participating in discussions on ... Proficiency in Object Oriented Programming, Verilog, System Verilog, UVM, SVA and functional ...
Lead Digital Verification Engineer
San Jose, CA · On-site
$159K - $194K/yr
... SVA), interfaces, and packages. * Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs. * Debug ...
Lead Digital Verification Engineer
San Jose, CA · On-site
$159K - $194K/yr
... SVA), interfaces, and packages. * Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs. * Debug ...
Senior ASIC Design Verification Engineer
Seattle, WA · On-site
$170K - $250K/yr
... designs. You will help define the verification approach, contribute to methodology, and work ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. * Drive ...
Senior ASIC Design Verification Engineer
Seattle, WA · On-site
$170K - $250K/yr
... designs. You will help define the verification approach, contribute to methodology, and work ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. * Drive ...
Principal ASIC Design Verification Engineer
$190K - $285K/yr
... designs. You will help define the verification approach, contribute to methodology, and work ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. * Drive ...
Principal ASIC Design Verification Engineer
$190K - $285K/yr
... designs. You will help define the verification approach, contribute to methodology, and work ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. * Drive ...
RTL Design Lead/IC Front-End Architect/Datapath Lead
San Jose, CA · On-site
$64.75 - $88.75/hr
Establish designer-level verification: block-level testbenches/sanity checks and assertion (SVA ... Comprehensive benefits package including health, dental, and vision * Professional development ...
RTL Design Lead/IC Front-End Architect/Datapath Lead
San Jose, CA · On-site
$64.75 - $88.75/hr
Establish designer-level verification: block-level testbenches/sanity checks and assertion (SVA ... Comprehensive benefits package including health, dental, and vision * Professional development ...
Principal ASIC Design Verification Engineer
Los Angeles, CA · On-site
$190K - $285K/yr
... designs. You will help define the verification approach, contribute to methodology, and work ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. * Drive ...
Principal ASIC Design Verification Engineer
Los Angeles, CA · On-site
$190K - $285K/yr
... designs. You will help define the verification approach, contribute to methodology, and work ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. * Drive ...
Senior ASIC Design Verification Engineer
$170K - $250K/yr
... designs. You will help define the verification approach, contribute to methodology, and work ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. * Drive ...
Senior ASIC Design Verification Engineer
$170K - $250K/yr
... designs. You will help define the verification approach, contribute to methodology, and work ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. * Drive ...
Digital Verification Engineer Prime (FEC)
Ottawa, ON · On-site
CA$133K - CA$212K/yr
... FEC designers, DSP modelers, FEC verifiers, systems engineers and architects. * You will be ... Significant experience in using C/C++, System Verilog, UVM, SVA, and simulators from major vendors.
Digital Verification Engineer Prime (FEC)
Ottawa, ON · On-site
CA$133K - CA$212K/yr
... FEC designers, DSP modelers, FEC verifiers, systems engineers and architects. * You will be ... Significant experience in using C/C++, System Verilog, UVM, SVA, and simulators from major vendors.
Senior Formal Verification Engineer - LPU
OR · On-site +1
Proficiency in SystemVerilog Assertions (SVA) and formal property verification. * Experience with ... benefits package. As you plan your future, see what we can offer to you and your family www ...
Senior Formal Verification Engineer - LPU
OR · On-site +1
Proficiency in SystemVerilog Assertions (SVA) and formal property verification. * Experience with ... benefits package. As you plan your future, see what we can offer to you and your family www ...
Principal ASIC Design Verification Engineer
Seattle, WA · On-site
$190K - $285K/yr
... designs. You will help define the verification approach, contribute to methodology, and work ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. * Drive ...
Principal ASIC Design Verification Engineer
Seattle, WA · On-site
$190K - $285K/yr
... designs. You will help define the verification approach, contribute to methodology, and work ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. * Drive ...
Senior ASIC Design Verification Engineer
Seattle, WA · On-site
$170K - $250K/yr
... designs. You will help define the verification approach, contribute to methodology, and work ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. * Drive ...
Senior ASIC Design Verification Engineer
Seattle, WA · On-site
$170K - $250K/yr
... designs. You will help define the verification approach, contribute to methodology, and work ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. * Drive ...
Proficiency in SystemVerilog Assertions (SVA) and formal property verification. * Experience with ... benefits package. As you plan your future, see what we can offer to you and your family www ...
Proficiency in SystemVerilog Assertions (SVA) and formal property verification. * Experience with ... benefits package. As you plan your future, see what we can offer to you and your family www ...
RTL Design Lead/IC Front-End Architect/Datapath Lead
San Jose, CA · On-site
$64.75 - $88.75/hr
Establish designer-level verification: block-level testbenches/sanity checks and assertion (SVA ... Comprehensive benefits package including health, dental, and vision * Professional development ...
RTL Design Lead/IC Front-End Architect/Datapath Lead
San Jose, CA · On-site
$64.75 - $88.75/hr
Establish designer-level verification: block-level testbenches/sanity checks and assertion (SVA ... Comprehensive benefits package including health, dental, and vision * Professional development ...
CA$133K - CA$212K/yr
... FEC designers, DSP modelers, FEC verifiers, systems engineers and architects. * You will be ... Significant experience in using C/C++, System Verilog, UVM, SVA, and simulators from major vendors.
CA$133K - CA$212K/yr
... FEC designers, DSP modelers, FEC verifiers, systems engineers and architects. * You will be ... Significant experience in using C/C++, System Verilog, UVM, SVA, and simulators from major vendors.
Principal ASIC Design Verification Engineer
$190K - $285K/yr
... designs. You will help define the verification approach, contribute to methodology, and work ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. * Drive ...
Principal ASIC Design Verification Engineer
$190K - $285K/yr
... designs. You will help define the verification approach, contribute to methodology, and work ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. * Drive ...
Senior Formal Verification Engineer - LPU
OR · On-site +1
Proficiency in SystemVerilog Assertions (SVA) and formal property verification. Experience with at ... benefits package. As you plan your future, see what we can offer to you and your family www ...
Senior Formal Verification Engineer - LPU
OR · On-site +1
Proficiency in SystemVerilog Assertions (SVA) and formal property verification. Experience with at ... benefits package. As you plan your future, see what we can offer to you and your family www ...
Create and maintain SystemVerilog Assertions (SVA) for 3D NAND designs based on verification ... In addition, Solidigm offers a benefits package that includes medical, dental, vision, supplemental ...
Create and maintain SystemVerilog Assertions (SVA) for 3D NAND designs based on verification ... In addition, Solidigm offers a benefits package that includes medical, dental, vision, supplemental ...
Design Verification Engineer
$146K - $178K/yr
The candidate must have experience using SystemVerilog and UVM, designing verification components ... Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)
Design Verification Engineer
$146K - $178K/yr
The candidate must have experience using SystemVerilog and UVM, designing verification components ... Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)
Design Verification Engineer
Mountain View, CA · On-site
$160K - $195K/yr
... and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our ... verify designs with SVA and industry leading formal tools * Develop tests using UVM or C/C+
Design Verification Engineer
Mountain View, CA · On-site
$160K - $195K/yr
... and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our ... verify designs with SVA and industry leading formal tools * Develop tests using UVM or C/C+
Design Verification Engineer
San Jose, CA · On-site
$159K - $194K/yr
The candidate must have experience using SystemVerilog and UVM, designing verification components ... Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)
Design Verification Engineer
San Jose, CA · On-site
$159K - $194K/yr
The candidate must have experience using SystemVerilog and UVM, designing verification components ... Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)
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Full-time
Re-posted 19 days ago
Nvidia rating
9.6
Based on 18 frontline employees who took The Breakroom Quiz
7th of 247 rated software companies
Job description
NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position offers you an outstanding opportunity to influence performance of the next generation GPU and SoC, allowing you to have real impact in a multifaceted, technology-focused company with product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of highly motivated people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
What you will be doing: Work as part of Circuit Solutions Group to develop various innovative IPs for hardware security, clocking, voltage regulation and silicon correlation. Own the unit and sub-system level verification of various IPs, create functional test plans, and verify using advanced verification tools, flows and methodologies. Build and reform world class verification infrastructure and methodologies to meet the unique demands of custom designed IPs.
Engage in design specification development by participating in discussions on architecture, intent, and implementation of the various IPs. Enable system level integration by working with partner teams for test development & debug and delivering Verification IPs. Play a key role in development and deployment of agentic AI frameworks for DV workflows such as stimulus generation, regression triage, debug, root cost analysis etc..
What we need to see: BSEE (or equivalent experience) with 5+ years' experience in unit level or sub-system level verification or MS preferred in Electrical, Computer Engineering with 3+ years' experience in unit level or sub-system level verification. Proficiency in Object Oriented Programming, Verilog, System Verilog, UVM, SVA and functional coverage development. Strong skills with VCS or equivalent simulation tools like Questa is required.
Strong debugging and analytical skills are required. Have a continuous improvement mentality and passionate about delivering bug-free first silicon. Ways to stand out from the crowd: Proficiency in developing and implementing agentic AI workflows using LLMs, Skills and industry standard agentic frameworks.
Strong knowledge or work experience in custom designed IPs solutions with good understanding of behavioral real number modeling of low level digital or mixed signal designs. Strong knowledge or work experience in co-simulation environments such as VCS-XA or equivalent tools, Gate Level Simulation or Formal Equivalence domains. Strong interpersonal skills and ability to work with on-site and remote teams.
Proficiency in scripting language, such as, Perl, Tcl, Make files and automation methods/algorithms a certain plus. With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We welcome you join our team with some of the most hard-working people in the world working together to promote rapid growth.
Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology. If so, we want to hear from you. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
The base salary range is 136,000 USD - 218,500 USD. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until July 31, 2026.
This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer.
As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US